1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH MSIOF SPI Controller Interface
4 *
5 * Copyright (c) 2009 Magnus Damm
6 * Copyright (C) 2014 Renesas Electronics Corporation
7 * Copyright (C) 2014-2017 Glider bvba
8 */
9
10 #include <linux/bitmap.h>
11 #include <linux/clk.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/sh_dma.h>
27
28 #include <linux/spi/sh_msiof.h>
29 #include <linux/spi/spi.h>
30
31 #include <asm/unaligned.h>
32
33 #define SH_MSIOF_FLAG_FIXED_DTDL_200 BIT(0)
34
35 struct sh_msiof_chipdata {
36 u32 bits_per_word_mask;
37 u16 tx_fifo_size;
38 u16 rx_fifo_size;
39 u16 ctlr_flags;
40 u16 min_div_pow;
41 u32 flags;
42 };
43
44 struct sh_msiof_spi_priv {
45 struct spi_controller *ctlr;
46 void __iomem *mapbase;
47 struct clk *clk;
48 struct platform_device *pdev;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 struct completion done_txdma;
52 unsigned int tx_fifo_size;
53 unsigned int rx_fifo_size;
54 unsigned int min_div_pow;
55 void *tx_dma_page;
56 void *rx_dma_page;
57 dma_addr_t tx_dma_addr;
58 dma_addr_t rx_dma_addr;
59 bool native_cs_inited;
60 bool native_cs_high;
61 bool slave_aborted;
62 };
63
64 #define MAX_SS 3 /* Maximum number of native chip selects */
65
66 #define SITMDR1 0x00 /* Transmit Mode Register 1 */
67 #define SITMDR2 0x04 /* Transmit Mode Register 2 */
68 #define SITMDR3 0x08 /* Transmit Mode Register 3 */
69 #define SIRMDR1 0x10 /* Receive Mode Register 1 */
70 #define SIRMDR2 0x14 /* Receive Mode Register 2 */
71 #define SIRMDR3 0x18 /* Receive Mode Register 3 */
72 #define SITSCR 0x20 /* Transmit Clock Select Register */
73 #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
74 #define SICTR 0x28 /* Control Register */
75 #define SIFCTR 0x30 /* FIFO Control Register */
76 #define SISTR 0x40 /* Status Register */
77 #define SIIER 0x44 /* Interrupt Enable Register */
78 #define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
79 #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
80 #define SITFDR 0x50 /* Transmit FIFO Data Register */
81 #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
82 #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
83 #define SIRFDR 0x60 /* Receive FIFO Data Register */
84
85 /* SITMDR1 and SIRMDR1 */
86 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
87 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
88 #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
89 #define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */
90 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
91 #define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
92 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
93 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
94 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
95 #define SIMDR1_FLD_SHIFT 2
96 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
97 /* SITMDR1 */
98 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
99 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
100 #define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
101
102 /* SITMDR2 and SIRMDR2 */
103 #define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
104 #define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
105 #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */
106
107 /* SITSCR and SIRSCR */
108 #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */
109 #define SISCR_BRPS(i) (((i) - 1) << 8)
110 #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */
111 #define SISCR_BRDV_DIV_2 0
112 #define SISCR_BRDV_DIV_4 1
113 #define SISCR_BRDV_DIV_8 2
114 #define SISCR_BRDV_DIV_16 3
115 #define SISCR_BRDV_DIV_32 4
116 #define SISCR_BRDV_DIV_1 7
117
118 /* SICTR */
119 #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */
120 #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */
121 #define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
122 #define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */
123 #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */
124 #define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
125 #define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
126 #define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
127 #define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */
128 #define SICTR_TXDIZ_LOW (0 << 22) /* 0 */
129 #define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */
130 #define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */
131 #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */
132 #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */
133 #define SICTR_TXE BIT(9) /* Transmit Enable */
134 #define SICTR_RXE BIT(8) /* Receive Enable */
135 #define SICTR_TXRST BIT(1) /* Transmit Reset */
136 #define SICTR_RXRST BIT(0) /* Receive Reset */
137
138 /* SIFCTR */
139 #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */
140 #define SIFCTR_TFWM_64 (0UL << 29) /* Transfer Request when 64 empty stages */
141 #define SIFCTR_TFWM_32 (1UL << 29) /* Transfer Request when 32 empty stages */
142 #define SIFCTR_TFWM_24 (2UL << 29) /* Transfer Request when 24 empty stages */
143 #define SIFCTR_TFWM_16 (3UL << 29) /* Transfer Request when 16 empty stages */
144 #define SIFCTR_TFWM_12 (4UL << 29) /* Transfer Request when 12 empty stages */
145 #define SIFCTR_TFWM_8 (5UL << 29) /* Transfer Request when 8 empty stages */
146 #define SIFCTR_TFWM_4 (6UL << 29) /* Transfer Request when 4 empty stages */
147 #define SIFCTR_TFWM_1 (7UL << 29) /* Transfer Request when 1 empty stage */
148 #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */
149 #define SIFCTR_TFUA_SHIFT 20
150 #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT)
151 #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */
152 #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */
153 #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */
154 #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */
155 #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */
156 #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */
157 #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */
158 #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */
159 #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */
160 #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */
161 #define SIFCTR_RFUA_SHIFT 4
162 #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT)
163
164 /* SISTR */
165 #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */
166 #define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */
167 #define SISTR_TEOF BIT(23) /* Frame Transmission End */
168 #define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */
169 #define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */
170 #define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */
171 #define SISTR_RFFUL BIT(13) /* Receive FIFO Full */
172 #define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */
173 #define SISTR_REOF BIT(7) /* Frame Reception End */
174 #define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */
175 #define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */
176 #define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */
177
178 /* SIIER */
179 #define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */
180 #define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */
181 #define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */
182 #define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */
183 #define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */
184 #define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */
185 #define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */
186 #define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */
187 #define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */
188 #define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */
189 #define SIIER_REOFE BIT(7) /* Frame Reception End Enable */
190 #define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */
191 #define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */
192 #define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */
193
194
sh_msiof_read(struct sh_msiof_spi_priv * p,int reg_offs)195 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
196 {
197 switch (reg_offs) {
198 case SITSCR:
199 case SIRSCR:
200 return ioread16(p->mapbase + reg_offs);
201 default:
202 return ioread32(p->mapbase + reg_offs);
203 }
204 }
205
sh_msiof_write(struct sh_msiof_spi_priv * p,int reg_offs,u32 value)206 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
207 u32 value)
208 {
209 switch (reg_offs) {
210 case SITSCR:
211 case SIRSCR:
212 iowrite16(value, p->mapbase + reg_offs);
213 break;
214 default:
215 iowrite32(value, p->mapbase + reg_offs);
216 break;
217 }
218 }
219
sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv * p,u32 clr,u32 set)220 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
221 u32 clr, u32 set)
222 {
223 u32 mask = clr | set;
224 u32 data;
225
226 data = sh_msiof_read(p, SICTR);
227 data &= ~clr;
228 data |= set;
229 sh_msiof_write(p, SICTR, data);
230
231 return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
232 (data & mask) == set, 1, 100);
233 }
234
sh_msiof_spi_irq(int irq,void * data)235 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
236 {
237 struct sh_msiof_spi_priv *p = data;
238
239 /* just disable the interrupt and wake up */
240 sh_msiof_write(p, SIIER, 0);
241 complete(&p->done);
242
243 return IRQ_HANDLED;
244 }
245
sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv * p)246 static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
247 {
248 u32 mask = SICTR_TXRST | SICTR_RXRST;
249 u32 data;
250
251 data = sh_msiof_read(p, SICTR);
252 data |= mask;
253 sh_msiof_write(p, SICTR, data);
254
255 readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
256 100);
257 }
258
259 static const u32 sh_msiof_spi_div_array[] = {
260 SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4,
261 SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32,
262 };
263
sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv * p,struct spi_transfer * t)264 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
265 struct spi_transfer *t)
266 {
267 unsigned long parent_rate = clk_get_rate(p->clk);
268 unsigned int div_pow = p->min_div_pow;
269 u32 spi_hz = t->speed_hz;
270 unsigned long div;
271 u32 brps, scr;
272
273 if (!spi_hz || !parent_rate) {
274 WARN(1, "Invalid clock rate parameters %lu and %u\n",
275 parent_rate, spi_hz);
276 return;
277 }
278
279 div = DIV_ROUND_UP(parent_rate, spi_hz);
280 if (div <= 1024) {
281 /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
282 if (!div_pow && div <= 32 && div > 2)
283 div_pow = 1;
284
285 if (div_pow)
286 brps = (div + 1) >> div_pow;
287 else
288 brps = div;
289
290 for (; brps > 32; div_pow++)
291 brps = (brps + 1) >> 1;
292 } else {
293 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
294 dev_err(&p->pdev->dev,
295 "Requested SPI transfer rate %d is too low\n", spi_hz);
296 div_pow = 5;
297 brps = 32;
298 }
299
300 t->effective_speed_hz = parent_rate / (brps << div_pow);
301
302 scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps);
303 sh_msiof_write(p, SITSCR, scr);
304 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
305 sh_msiof_write(p, SIRSCR, scr);
306 }
307
sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)308 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
309 {
310 /*
311 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
312 * b'000 : 0
313 * b'001 : 100
314 * b'010 : 200
315 * b'011 (SYNCDL only) : 300
316 * b'101 : 50
317 * b'110 : 150
318 */
319 if (dtdl_or_syncdl % 100)
320 return dtdl_or_syncdl / 100 + 5;
321 else
322 return dtdl_or_syncdl / 100;
323 }
324
sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv * p)325 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
326 {
327 u32 val;
328
329 if (!p->info)
330 return 0;
331
332 /* check if DTDL and SYNCDL is allowed value */
333 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
334 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
335 return 0;
336 }
337
338 /* check if the sum of DTDL and SYNCDL becomes an integer value */
339 if ((p->info->dtdl + p->info->syncdl) % 100) {
340 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
341 return 0;
342 }
343
344 val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
345 val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
346
347 return val;
348 }
349
sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv * p,u32 ss,u32 cpol,u32 cpha,u32 tx_hi_z,u32 lsb_first,u32 cs_high)350 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
351 u32 cpol, u32 cpha,
352 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
353 {
354 u32 tmp;
355 int edge;
356
357 /*
358 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
359 * 0 0 10 10 1 1
360 * 0 1 10 10 0 0
361 * 1 0 11 11 0 0
362 * 1 1 11 11 1 1
363 */
364 tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
365 tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
366 tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
367 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
368 if (spi_controller_is_slave(p->ctlr)) {
369 sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
370 } else {
371 sh_msiof_write(p, SITMDR1,
372 tmp | SIMDR1_TRMD | SITMDR1_PCON |
373 (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
374 }
375 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
376 /* These bits are reserved if RX needs TX */
377 tmp &= ~0x0000ffff;
378 }
379 sh_msiof_write(p, SIRMDR1, tmp);
380
381 tmp = 0;
382 tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT;
383 tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT;
384
385 edge = cpol ^ !cpha;
386
387 tmp |= edge << SICTR_TEDG_SHIFT;
388 tmp |= edge << SICTR_REDG_SHIFT;
389 tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW;
390 sh_msiof_write(p, SICTR, tmp);
391 }
392
sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv * p,const void * tx_buf,void * rx_buf,u32 bits,u32 words)393 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
394 const void *tx_buf, void *rx_buf,
395 u32 bits, u32 words)
396 {
397 u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words);
398
399 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX))
400 sh_msiof_write(p, SITMDR2, dr2);
401 else
402 sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1);
403
404 if (rx_buf)
405 sh_msiof_write(p, SIRMDR2, dr2);
406 }
407
sh_msiof_reset_str(struct sh_msiof_spi_priv * p)408 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
409 {
410 sh_msiof_write(p, SISTR,
411 sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ));
412 }
413
sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)414 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
415 const void *tx_buf, int words, int fs)
416 {
417 const u8 *buf_8 = tx_buf;
418 int k;
419
420 for (k = 0; k < words; k++)
421 sh_msiof_write(p, SITFDR, buf_8[k] << fs);
422 }
423
sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)424 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
425 const void *tx_buf, int words, int fs)
426 {
427 const u16 *buf_16 = tx_buf;
428 int k;
429
430 for (k = 0; k < words; k++)
431 sh_msiof_write(p, SITFDR, buf_16[k] << fs);
432 }
433
sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)434 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
435 const void *tx_buf, int words, int fs)
436 {
437 const u16 *buf_16 = tx_buf;
438 int k;
439
440 for (k = 0; k < words; k++)
441 sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);
442 }
443
sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)444 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
445 const void *tx_buf, int words, int fs)
446 {
447 const u32 *buf_32 = tx_buf;
448 int k;
449
450 for (k = 0; k < words; k++)
451 sh_msiof_write(p, SITFDR, buf_32[k] << fs);
452 }
453
sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)454 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
455 const void *tx_buf, int words, int fs)
456 {
457 const u32 *buf_32 = tx_buf;
458 int k;
459
460 for (k = 0; k < words; k++)
461 sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);
462 }
463
sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)464 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
465 const void *tx_buf, int words, int fs)
466 {
467 const u32 *buf_32 = tx_buf;
468 int k;
469
470 for (k = 0; k < words; k++)
471 sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));
472 }
473
sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv * p,const void * tx_buf,int words,int fs)474 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
475 const void *tx_buf, int words, int fs)
476 {
477 const u32 *buf_32 = tx_buf;
478 int k;
479
480 for (k = 0; k < words; k++)
481 sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));
482 }
483
sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)484 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
485 void *rx_buf, int words, int fs)
486 {
487 u8 *buf_8 = rx_buf;
488 int k;
489
490 for (k = 0; k < words; k++)
491 buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;
492 }
493
sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)494 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
495 void *rx_buf, int words, int fs)
496 {
497 u16 *buf_16 = rx_buf;
498 int k;
499
500 for (k = 0; k < words; k++)
501 buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;
502 }
503
sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)504 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
505 void *rx_buf, int words, int fs)
506 {
507 u16 *buf_16 = rx_buf;
508 int k;
509
510 for (k = 0; k < words; k++)
511 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);
512 }
513
sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)514 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
515 void *rx_buf, int words, int fs)
516 {
517 u32 *buf_32 = rx_buf;
518 int k;
519
520 for (k = 0; k < words; k++)
521 buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;
522 }
523
sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)524 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
525 void *rx_buf, int words, int fs)
526 {
527 u32 *buf_32 = rx_buf;
528 int k;
529
530 for (k = 0; k < words; k++)
531 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);
532 }
533
sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)534 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
535 void *rx_buf, int words, int fs)
536 {
537 u32 *buf_32 = rx_buf;
538 int k;
539
540 for (k = 0; k < words; k++)
541 buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);
542 }
543
sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv * p,void * rx_buf,int words,int fs)544 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
545 void *rx_buf, int words, int fs)
546 {
547 u32 *buf_32 = rx_buf;
548 int k;
549
550 for (k = 0; k < words; k++)
551 put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);
552 }
553
sh_msiof_spi_setup(struct spi_device * spi)554 static int sh_msiof_spi_setup(struct spi_device *spi)
555 {
556 struct sh_msiof_spi_priv *p =
557 spi_controller_get_devdata(spi->controller);
558 u32 clr, set, tmp;
559
560 if (spi->cs_gpiod || spi_controller_is_slave(p->ctlr))
561 return 0;
562
563 if (p->native_cs_inited &&
564 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
565 return 0;
566
567 /* Configure native chip select mode/polarity early */
568 clr = SIMDR1_SYNCMD_MASK;
569 set = SIMDR1_SYNCMD_SPI;
570 if (spi->mode & SPI_CS_HIGH)
571 clr |= BIT(SIMDR1_SYNCAC_SHIFT);
572 else
573 set |= BIT(SIMDR1_SYNCAC_SHIFT);
574 pm_runtime_get_sync(&p->pdev->dev);
575 tmp = sh_msiof_read(p, SITMDR1) & ~clr;
576 sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
577 tmp = sh_msiof_read(p, SIRMDR1) & ~clr;
578 sh_msiof_write(p, SIRMDR1, tmp | set);
579 pm_runtime_put(&p->pdev->dev);
580 p->native_cs_high = spi->mode & SPI_CS_HIGH;
581 p->native_cs_inited = true;
582 return 0;
583 }
584
sh_msiof_prepare_message(struct spi_controller * ctlr,struct spi_message * msg)585 static int sh_msiof_prepare_message(struct spi_controller *ctlr,
586 struct spi_message *msg)
587 {
588 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
589 const struct spi_device *spi = msg->spi;
590 u32 ss, cs_high;
591
592 /* Configure pins before asserting CS */
593 if (spi->cs_gpiod) {
594 ss = ctlr->unused_native_cs;
595 cs_high = p->native_cs_high;
596 } else {
597 ss = spi->chip_select;
598 cs_high = !!(spi->mode & SPI_CS_HIGH);
599 }
600 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL),
601 !!(spi->mode & SPI_CPHA),
602 !!(spi->mode & SPI_3WIRE),
603 !!(spi->mode & SPI_LSB_FIRST), cs_high);
604 return 0;
605 }
606
sh_msiof_spi_start(struct sh_msiof_spi_priv * p,void * rx_buf)607 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
608 {
609 bool slave = spi_controller_is_slave(p->ctlr);
610 int ret = 0;
611
612 /* setup clock and rx/tx signals */
613 if (!slave)
614 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE);
615 if (rx_buf && !ret)
616 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE);
617 if (!ret)
618 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE);
619
620 /* start by setting frame bit */
621 if (!ret && !slave)
622 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE);
623
624 return ret;
625 }
626
sh_msiof_spi_stop(struct sh_msiof_spi_priv * p,void * rx_buf)627 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
628 {
629 bool slave = spi_controller_is_slave(p->ctlr);
630 int ret = 0;
631
632 /* shut down frame, rx/tx and clock signals */
633 if (!slave)
634 ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0);
635 if (!ret)
636 ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0);
637 if (rx_buf && !ret)
638 ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0);
639 if (!ret && !slave)
640 ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0);
641
642 return ret;
643 }
644
sh_msiof_slave_abort(struct spi_controller * ctlr)645 static int sh_msiof_slave_abort(struct spi_controller *ctlr)
646 {
647 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
648
649 p->slave_aborted = true;
650 complete(&p->done);
651 complete(&p->done_txdma);
652 return 0;
653 }
654
sh_msiof_wait_for_completion(struct sh_msiof_spi_priv * p,struct completion * x)655 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p,
656 struct completion *x)
657 {
658 if (spi_controller_is_slave(p->ctlr)) {
659 if (wait_for_completion_interruptible(x) ||
660 p->slave_aborted) {
661 dev_dbg(&p->pdev->dev, "interrupted\n");
662 return -EINTR;
663 }
664 } else {
665 if (!wait_for_completion_timeout(x, HZ)) {
666 dev_err(&p->pdev->dev, "timeout\n");
667 return -ETIMEDOUT;
668 }
669 }
670
671 return 0;
672 }
673
sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv * p,void (* tx_fifo)(struct sh_msiof_spi_priv *,const void *,int,int),void (* rx_fifo)(struct sh_msiof_spi_priv *,void *,int,int),const void * tx_buf,void * rx_buf,int words,int bits)674 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
675 void (*tx_fifo)(struct sh_msiof_spi_priv *,
676 const void *, int, int),
677 void (*rx_fifo)(struct sh_msiof_spi_priv *,
678 void *, int, int),
679 const void *tx_buf, void *rx_buf,
680 int words, int bits)
681 {
682 int fifo_shift;
683 int ret;
684
685 /* limit maximum word transfer to rx/tx fifo size */
686 if (tx_buf)
687 words = min_t(int, words, p->tx_fifo_size);
688 if (rx_buf)
689 words = min_t(int, words, p->rx_fifo_size);
690
691 /* the fifo contents need shifting */
692 fifo_shift = 32 - bits;
693
694 /* default FIFO watermarks for PIO */
695 sh_msiof_write(p, SIFCTR, 0);
696
697 /* setup msiof transfer mode registers */
698 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
699 sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE);
700
701 /* write tx fifo */
702 if (tx_buf)
703 tx_fifo(p, tx_buf, words, fifo_shift);
704
705 reinit_completion(&p->done);
706 p->slave_aborted = false;
707
708 ret = sh_msiof_spi_start(p, rx_buf);
709 if (ret) {
710 dev_err(&p->pdev->dev, "failed to start hardware\n");
711 goto stop_ier;
712 }
713
714 /* wait for tx fifo to be emptied / rx fifo to be filled */
715 ret = sh_msiof_wait_for_completion(p, &p->done);
716 if (ret)
717 goto stop_reset;
718
719 /* read rx fifo */
720 if (rx_buf)
721 rx_fifo(p, rx_buf, words, fifo_shift);
722
723 /* clear status bits */
724 sh_msiof_reset_str(p);
725
726 ret = sh_msiof_spi_stop(p, rx_buf);
727 if (ret) {
728 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
729 return ret;
730 }
731
732 return words;
733
734 stop_reset:
735 sh_msiof_reset_str(p);
736 sh_msiof_spi_stop(p, rx_buf);
737 stop_ier:
738 sh_msiof_write(p, SIIER, 0);
739 return ret;
740 }
741
sh_msiof_dma_complete(void * arg)742 static void sh_msiof_dma_complete(void *arg)
743 {
744 complete(arg);
745 }
746
sh_msiof_dma_once(struct sh_msiof_spi_priv * p,const void * tx,void * rx,unsigned int len)747 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
748 void *rx, unsigned int len)
749 {
750 u32 ier_bits = 0;
751 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
752 dma_cookie_t cookie;
753 int ret;
754
755 /* First prepare and submit the DMA request(s), as this may fail */
756 if (rx) {
757 ier_bits |= SIIER_RDREQE | SIIER_RDMAE;
758 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx,
759 p->rx_dma_addr, len, DMA_DEV_TO_MEM,
760 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
761 if (!desc_rx)
762 return -EAGAIN;
763
764 desc_rx->callback = sh_msiof_dma_complete;
765 desc_rx->callback_param = &p->done;
766 cookie = dmaengine_submit(desc_rx);
767 if (dma_submit_error(cookie))
768 return cookie;
769 }
770
771 if (tx) {
772 ier_bits |= SIIER_TDREQE | SIIER_TDMAE;
773 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev,
774 p->tx_dma_addr, len, DMA_TO_DEVICE);
775 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx,
776 p->tx_dma_addr, len, DMA_MEM_TO_DEV,
777 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
778 if (!desc_tx) {
779 ret = -EAGAIN;
780 goto no_dma_tx;
781 }
782
783 desc_tx->callback = sh_msiof_dma_complete;
784 desc_tx->callback_param = &p->done_txdma;
785 cookie = dmaengine_submit(desc_tx);
786 if (dma_submit_error(cookie)) {
787 ret = cookie;
788 goto no_dma_tx;
789 }
790 }
791
792 /* 1 stage FIFO watermarks for DMA */
793 sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1);
794
795 /* setup msiof transfer mode registers (32-bit words) */
796 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
797
798 sh_msiof_write(p, SIIER, ier_bits);
799
800 reinit_completion(&p->done);
801 if (tx)
802 reinit_completion(&p->done_txdma);
803 p->slave_aborted = false;
804
805 /* Now start DMA */
806 if (rx)
807 dma_async_issue_pending(p->ctlr->dma_rx);
808 if (tx)
809 dma_async_issue_pending(p->ctlr->dma_tx);
810
811 ret = sh_msiof_spi_start(p, rx);
812 if (ret) {
813 dev_err(&p->pdev->dev, "failed to start hardware\n");
814 goto stop_dma;
815 }
816
817 if (tx) {
818 /* wait for tx DMA completion */
819 ret = sh_msiof_wait_for_completion(p, &p->done_txdma);
820 if (ret)
821 goto stop_reset;
822 }
823
824 if (rx) {
825 /* wait for rx DMA completion */
826 ret = sh_msiof_wait_for_completion(p, &p->done);
827 if (ret)
828 goto stop_reset;
829
830 sh_msiof_write(p, SIIER, 0);
831 } else {
832 /* wait for tx fifo to be emptied */
833 sh_msiof_write(p, SIIER, SIIER_TEOFE);
834 ret = sh_msiof_wait_for_completion(p, &p->done);
835 if (ret)
836 goto stop_reset;
837 }
838
839 /* clear status bits */
840 sh_msiof_reset_str(p);
841
842 ret = sh_msiof_spi_stop(p, rx);
843 if (ret) {
844 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
845 return ret;
846 }
847
848 if (rx)
849 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev,
850 p->rx_dma_addr, len, DMA_FROM_DEVICE);
851
852 return 0;
853
854 stop_reset:
855 sh_msiof_reset_str(p);
856 sh_msiof_spi_stop(p, rx);
857 stop_dma:
858 if (tx)
859 dmaengine_terminate_sync(p->ctlr->dma_tx);
860 no_dma_tx:
861 if (rx)
862 dmaengine_terminate_sync(p->ctlr->dma_rx);
863 sh_msiof_write(p, SIIER, 0);
864 return ret;
865 }
866
copy_bswap32(u32 * dst,const u32 * src,unsigned int words)867 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
868 {
869 /* src or dst can be unaligned, but not both */
870 if ((unsigned long)src & 3) {
871 while (words--) {
872 *dst++ = swab32(get_unaligned(src));
873 src++;
874 }
875 } else if ((unsigned long)dst & 3) {
876 while (words--) {
877 put_unaligned(swab32(*src++), dst);
878 dst++;
879 }
880 } else {
881 while (words--)
882 *dst++ = swab32(*src++);
883 }
884 }
885
copy_wswap32(u32 * dst,const u32 * src,unsigned int words)886 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
887 {
888 /* src or dst can be unaligned, but not both */
889 if ((unsigned long)src & 3) {
890 while (words--) {
891 *dst++ = swahw32(get_unaligned(src));
892 src++;
893 }
894 } else if ((unsigned long)dst & 3) {
895 while (words--) {
896 put_unaligned(swahw32(*src++), dst);
897 dst++;
898 }
899 } else {
900 while (words--)
901 *dst++ = swahw32(*src++);
902 }
903 }
904
copy_plain32(u32 * dst,const u32 * src,unsigned int words)905 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
906 {
907 memcpy(dst, src, words * 4);
908 }
909
sh_msiof_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * t)910 static int sh_msiof_transfer_one(struct spi_controller *ctlr,
911 struct spi_device *spi,
912 struct spi_transfer *t)
913 {
914 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr);
915 void (*copy32)(u32 *, const u32 *, unsigned int);
916 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
917 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
918 const void *tx_buf = t->tx_buf;
919 void *rx_buf = t->rx_buf;
920 unsigned int len = t->len;
921 unsigned int bits = t->bits_per_word;
922 unsigned int bytes_per_word;
923 unsigned int words;
924 int n;
925 bool swab;
926 int ret;
927
928 /* reset registers */
929 sh_msiof_spi_reset_regs(p);
930
931 /* setup clocks (clock already enabled in chipselect()) */
932 if (!spi_controller_is_slave(p->ctlr))
933 sh_msiof_spi_set_clk_regs(p, t);
934
935 while (ctlr->dma_tx && len > 15) {
936 /*
937 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
938 * words, with byte resp. word swapping.
939 */
940 unsigned int l = 0;
941
942 if (tx_buf)
943 l = min(round_down(len, 4), p->tx_fifo_size * 4);
944 if (rx_buf)
945 l = min(round_down(len, 4), p->rx_fifo_size * 4);
946
947 if (bits <= 8) {
948 copy32 = copy_bswap32;
949 } else if (bits <= 16) {
950 copy32 = copy_wswap32;
951 } else {
952 copy32 = copy_plain32;
953 }
954
955 if (tx_buf)
956 copy32(p->tx_dma_page, tx_buf, l / 4);
957
958 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
959 if (ret == -EAGAIN) {
960 dev_warn_once(&p->pdev->dev,
961 "DMA not available, falling back to PIO\n");
962 break;
963 }
964 if (ret)
965 return ret;
966
967 if (rx_buf) {
968 copy32(rx_buf, p->rx_dma_page, l / 4);
969 rx_buf += l;
970 }
971 if (tx_buf)
972 tx_buf += l;
973
974 len -= l;
975 if (!len)
976 return 0;
977 }
978
979 if (bits <= 8 && len > 15) {
980 bits = 32;
981 swab = true;
982 } else {
983 swab = false;
984 }
985
986 /* setup bytes per word and fifo read/write functions */
987 if (bits <= 8) {
988 bytes_per_word = 1;
989 tx_fifo = sh_msiof_spi_write_fifo_8;
990 rx_fifo = sh_msiof_spi_read_fifo_8;
991 } else if (bits <= 16) {
992 bytes_per_word = 2;
993 if ((unsigned long)tx_buf & 0x01)
994 tx_fifo = sh_msiof_spi_write_fifo_16u;
995 else
996 tx_fifo = sh_msiof_spi_write_fifo_16;
997
998 if ((unsigned long)rx_buf & 0x01)
999 rx_fifo = sh_msiof_spi_read_fifo_16u;
1000 else
1001 rx_fifo = sh_msiof_spi_read_fifo_16;
1002 } else if (swab) {
1003 bytes_per_word = 4;
1004 if ((unsigned long)tx_buf & 0x03)
1005 tx_fifo = sh_msiof_spi_write_fifo_s32u;
1006 else
1007 tx_fifo = sh_msiof_spi_write_fifo_s32;
1008
1009 if ((unsigned long)rx_buf & 0x03)
1010 rx_fifo = sh_msiof_spi_read_fifo_s32u;
1011 else
1012 rx_fifo = sh_msiof_spi_read_fifo_s32;
1013 } else {
1014 bytes_per_word = 4;
1015 if ((unsigned long)tx_buf & 0x03)
1016 tx_fifo = sh_msiof_spi_write_fifo_32u;
1017 else
1018 tx_fifo = sh_msiof_spi_write_fifo_32;
1019
1020 if ((unsigned long)rx_buf & 0x03)
1021 rx_fifo = sh_msiof_spi_read_fifo_32u;
1022 else
1023 rx_fifo = sh_msiof_spi_read_fifo_32;
1024 }
1025
1026 /* transfer in fifo sized chunks */
1027 words = len / bytes_per_word;
1028
1029 while (words > 0) {
1030 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1031 words, bits);
1032 if (n < 0)
1033 return n;
1034
1035 if (tx_buf)
1036 tx_buf += n * bytes_per_word;
1037 if (rx_buf)
1038 rx_buf += n * bytes_per_word;
1039 words -= n;
1040
1041 if (words == 0 && (len % bytes_per_word)) {
1042 words = len % bytes_per_word;
1043 bits = t->bits_per_word;
1044 bytes_per_word = 1;
1045 tx_fifo = sh_msiof_spi_write_fifo_8;
1046 rx_fifo = sh_msiof_spi_read_fifo_8;
1047 }
1048 }
1049
1050 return 0;
1051 }
1052
1053 static const struct sh_msiof_chipdata sh_data = {
1054 .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1055 .tx_fifo_size = 64,
1056 .rx_fifo_size = 64,
1057 .ctlr_flags = 0,
1058 .min_div_pow = 0,
1059 };
1060
1061 static const struct sh_msiof_chipdata rcar_gen2_data = {
1062 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1063 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1064 .tx_fifo_size = 64,
1065 .rx_fifo_size = 64,
1066 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1067 .min_div_pow = 0,
1068 };
1069
1070 static const struct sh_msiof_chipdata rcar_gen3_data = {
1071 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1072 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1073 .tx_fifo_size = 64,
1074 .rx_fifo_size = 64,
1075 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1076 .min_div_pow = 1,
1077 };
1078
1079 static const struct sh_msiof_chipdata rcar_r8a7795_data = {
1080 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1081 SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1082 .tx_fifo_size = 64,
1083 .rx_fifo_size = 64,
1084 .ctlr_flags = SPI_CONTROLLER_MUST_TX,
1085 .min_div_pow = 1,
1086 .flags = SH_MSIOF_FLAG_FIXED_DTDL_200,
1087 };
1088
1089 static const struct of_device_id sh_msiof_match[] = {
1090 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1091 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1092 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1093 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1094 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1095 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1096 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1097 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1098 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1099 { .compatible = "renesas,msiof-r8a7795", .data = &rcar_r8a7795_data },
1100 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1101 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1102 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1103 {},
1104 };
1105 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1106
1107 #ifdef CONFIG_OF
sh_msiof_spi_parse_dt(struct device * dev)1108 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1109 {
1110 struct sh_msiof_spi_info *info;
1111 struct device_node *np = dev->of_node;
1112 u32 num_cs = 1;
1113
1114 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1115 if (!info)
1116 return NULL;
1117
1118 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1119 : MSIOF_SPI_MASTER;
1120
1121 /* Parse the MSIOF properties */
1122 if (info->mode == MSIOF_SPI_MASTER)
1123 of_property_read_u32(np, "num-cs", &num_cs);
1124 of_property_read_u32(np, "renesas,tx-fifo-size",
1125 &info->tx_fifo_override);
1126 of_property_read_u32(np, "renesas,rx-fifo-size",
1127 &info->rx_fifo_override);
1128 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1129 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1130
1131 info->num_chipselect = num_cs;
1132
1133 return info;
1134 }
1135 #else
sh_msiof_spi_parse_dt(struct device * dev)1136 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1137 {
1138 return NULL;
1139 }
1140 #endif
1141
sh_msiof_request_dma_chan(struct device * dev,enum dma_transfer_direction dir,unsigned int id,dma_addr_t port_addr)1142 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1143 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1144 {
1145 dma_cap_mask_t mask;
1146 struct dma_chan *chan;
1147 struct dma_slave_config cfg;
1148 int ret;
1149
1150 dma_cap_zero(mask);
1151 dma_cap_set(DMA_SLAVE, mask);
1152
1153 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1154 (void *)(unsigned long)id, dev,
1155 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1156 if (!chan) {
1157 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1158 return NULL;
1159 }
1160
1161 memset(&cfg, 0, sizeof(cfg));
1162 cfg.direction = dir;
1163 if (dir == DMA_MEM_TO_DEV) {
1164 cfg.dst_addr = port_addr;
1165 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1166 } else {
1167 cfg.src_addr = port_addr;
1168 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1169 }
1170
1171 ret = dmaengine_slave_config(chan, &cfg);
1172 if (ret) {
1173 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1174 dma_release_channel(chan);
1175 return NULL;
1176 }
1177
1178 return chan;
1179 }
1180
sh_msiof_request_dma(struct sh_msiof_spi_priv * p)1181 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1182 {
1183 struct platform_device *pdev = p->pdev;
1184 struct device *dev = &pdev->dev;
1185 const struct sh_msiof_spi_info *info = p->info;
1186 unsigned int dma_tx_id, dma_rx_id;
1187 const struct resource *res;
1188 struct spi_controller *ctlr;
1189 struct device *tx_dev, *rx_dev;
1190
1191 if (dev->of_node) {
1192 /* In the OF case we will get the slave IDs from the DT */
1193 dma_tx_id = 0;
1194 dma_rx_id = 0;
1195 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1196 dma_tx_id = info->dma_tx_id;
1197 dma_rx_id = info->dma_rx_id;
1198 } else {
1199 /* The driver assumes no error */
1200 return 0;
1201 }
1202
1203 /* The DMA engine uses the second register set, if present */
1204 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1205 if (!res)
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1207
1208 ctlr = p->ctlr;
1209 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1210 dma_tx_id, res->start + SITFDR);
1211 if (!ctlr->dma_tx)
1212 return -ENODEV;
1213
1214 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1215 dma_rx_id, res->start + SIRFDR);
1216 if (!ctlr->dma_rx)
1217 goto free_tx_chan;
1218
1219 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1220 if (!p->tx_dma_page)
1221 goto free_rx_chan;
1222
1223 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1224 if (!p->rx_dma_page)
1225 goto free_tx_page;
1226
1227 tx_dev = ctlr->dma_tx->device->dev;
1228 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1229 DMA_TO_DEVICE);
1230 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1231 goto free_rx_page;
1232
1233 rx_dev = ctlr->dma_rx->device->dev;
1234 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1235 DMA_FROM_DEVICE);
1236 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1237 goto unmap_tx_page;
1238
1239 dev_info(dev, "DMA available");
1240 return 0;
1241
1242 unmap_tx_page:
1243 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1244 free_rx_page:
1245 free_page((unsigned long)p->rx_dma_page);
1246 free_tx_page:
1247 free_page((unsigned long)p->tx_dma_page);
1248 free_rx_chan:
1249 dma_release_channel(ctlr->dma_rx);
1250 free_tx_chan:
1251 dma_release_channel(ctlr->dma_tx);
1252 ctlr->dma_tx = NULL;
1253 return -ENODEV;
1254 }
1255
sh_msiof_release_dma(struct sh_msiof_spi_priv * p)1256 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1257 {
1258 struct spi_controller *ctlr = p->ctlr;
1259
1260 if (!ctlr->dma_tx)
1261 return;
1262
1263 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE,
1264 DMA_FROM_DEVICE);
1265 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE,
1266 DMA_TO_DEVICE);
1267 free_page((unsigned long)p->rx_dma_page);
1268 free_page((unsigned long)p->tx_dma_page);
1269 dma_release_channel(ctlr->dma_rx);
1270 dma_release_channel(ctlr->dma_tx);
1271 }
1272
sh_msiof_spi_probe(struct platform_device * pdev)1273 static int sh_msiof_spi_probe(struct platform_device *pdev)
1274 {
1275 struct spi_controller *ctlr;
1276 const struct sh_msiof_chipdata *chipdata;
1277 struct sh_msiof_spi_info *info;
1278 struct sh_msiof_spi_priv *p;
1279 unsigned long clksrc;
1280 int i;
1281 int ret;
1282
1283 chipdata = of_device_get_match_data(&pdev->dev);
1284 if (chipdata) {
1285 info = sh_msiof_spi_parse_dt(&pdev->dev);
1286 } else {
1287 chipdata = (const void *)pdev->id_entry->driver_data;
1288 info = dev_get_platdata(&pdev->dev);
1289 }
1290
1291 if (!info) {
1292 dev_err(&pdev->dev, "failed to obtain device info\n");
1293 return -ENXIO;
1294 }
1295
1296 if (chipdata->flags & SH_MSIOF_FLAG_FIXED_DTDL_200)
1297 info->dtdl = 200;
1298
1299 if (info->mode == MSIOF_SPI_SLAVE)
1300 ctlr = spi_alloc_slave(&pdev->dev,
1301 sizeof(struct sh_msiof_spi_priv));
1302 else
1303 ctlr = spi_alloc_master(&pdev->dev,
1304 sizeof(struct sh_msiof_spi_priv));
1305 if (ctlr == NULL)
1306 return -ENOMEM;
1307
1308 p = spi_controller_get_devdata(ctlr);
1309
1310 platform_set_drvdata(pdev, p);
1311 p->ctlr = ctlr;
1312 p->info = info;
1313 p->min_div_pow = chipdata->min_div_pow;
1314
1315 init_completion(&p->done);
1316 init_completion(&p->done_txdma);
1317
1318 p->clk = devm_clk_get(&pdev->dev, NULL);
1319 if (IS_ERR(p->clk)) {
1320 dev_err(&pdev->dev, "cannot get clock\n");
1321 ret = PTR_ERR(p->clk);
1322 goto err1;
1323 }
1324
1325 i = platform_get_irq(pdev, 0);
1326 if (i < 0) {
1327 ret = i;
1328 goto err1;
1329 }
1330
1331 p->mapbase = devm_platform_ioremap_resource(pdev, 0);
1332 if (IS_ERR(p->mapbase)) {
1333 ret = PTR_ERR(p->mapbase);
1334 goto err1;
1335 }
1336
1337 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1338 dev_name(&pdev->dev), p);
1339 if (ret) {
1340 dev_err(&pdev->dev, "unable to request irq\n");
1341 goto err1;
1342 }
1343
1344 p->pdev = pdev;
1345 pm_runtime_enable(&pdev->dev);
1346
1347 /* Platform data may override FIFO sizes */
1348 p->tx_fifo_size = chipdata->tx_fifo_size;
1349 p->rx_fifo_size = chipdata->rx_fifo_size;
1350 if (p->info->tx_fifo_override)
1351 p->tx_fifo_size = p->info->tx_fifo_override;
1352 if (p->info->rx_fifo_override)
1353 p->rx_fifo_size = p->info->rx_fifo_override;
1354
1355 /* init controller code */
1356 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1357 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1358 clksrc = clk_get_rate(p->clk);
1359 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024);
1360 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow);
1361 ctlr->flags = chipdata->ctlr_flags;
1362 ctlr->bus_num = pdev->id;
1363 ctlr->num_chipselect = p->info->num_chipselect;
1364 ctlr->dev.of_node = pdev->dev.of_node;
1365 ctlr->setup = sh_msiof_spi_setup;
1366 ctlr->prepare_message = sh_msiof_prepare_message;
1367 ctlr->slave_abort = sh_msiof_slave_abort;
1368 ctlr->bits_per_word_mask = chipdata->bits_per_word_mask;
1369 ctlr->auto_runtime_pm = true;
1370 ctlr->transfer_one = sh_msiof_transfer_one;
1371 ctlr->use_gpio_descriptors = true;
1372 ctlr->max_native_cs = MAX_SS;
1373
1374 ret = sh_msiof_request_dma(p);
1375 if (ret < 0)
1376 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1377
1378 ret = devm_spi_register_controller(&pdev->dev, ctlr);
1379 if (ret < 0) {
1380 dev_err(&pdev->dev, "devm_spi_register_controller error.\n");
1381 goto err2;
1382 }
1383
1384 return 0;
1385
1386 err2:
1387 sh_msiof_release_dma(p);
1388 pm_runtime_disable(&pdev->dev);
1389 err1:
1390 spi_controller_put(ctlr);
1391 return ret;
1392 }
1393
sh_msiof_spi_remove(struct platform_device * pdev)1394 static int sh_msiof_spi_remove(struct platform_device *pdev)
1395 {
1396 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1397
1398 sh_msiof_release_dma(p);
1399 pm_runtime_disable(&pdev->dev);
1400 return 0;
1401 }
1402
1403 static const struct platform_device_id spi_driver_ids[] = {
1404 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1405 {},
1406 };
1407 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1408
1409 #ifdef CONFIG_PM_SLEEP
sh_msiof_spi_suspend(struct device * dev)1410 static int sh_msiof_spi_suspend(struct device *dev)
1411 {
1412 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1413
1414 return spi_controller_suspend(p->ctlr);
1415 }
1416
sh_msiof_spi_resume(struct device * dev)1417 static int sh_msiof_spi_resume(struct device *dev)
1418 {
1419 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);
1420
1421 return spi_controller_resume(p->ctlr);
1422 }
1423
1424 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend,
1425 sh_msiof_spi_resume);
1426 #define DEV_PM_OPS (&sh_msiof_spi_pm_ops)
1427 #else
1428 #define DEV_PM_OPS NULL
1429 #endif /* CONFIG_PM_SLEEP */
1430
1431 static struct platform_driver sh_msiof_spi_drv = {
1432 .probe = sh_msiof_spi_probe,
1433 .remove = sh_msiof_spi_remove,
1434 .id_table = spi_driver_ids,
1435 .driver = {
1436 .name = "spi_sh_msiof",
1437 .pm = DEV_PM_OPS,
1438 .of_match_table = of_match_ptr(sh_msiof_match),
1439 },
1440 };
1441 module_platform_driver(sh_msiof_spi_drv);
1442
1443 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver");
1444 MODULE_AUTHOR("Magnus Damm");
1445 MODULE_LICENSE("GPL v2");
1446 MODULE_ALIAS("platform:spi_sh_msiof");
1447