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Searched refs:SRII (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
66 SRII(MODULO, DP_DTO, 0),\
67 SRII(MODULO, DP_DTO, 1),\
68 SRII(MODULO, DP_DTO, 2),\
69 SRII(MODULO, DP_DTO, 3),\
[all …]
Ddce_hwseq.h39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \
40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \
41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \
42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \
43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \
44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \
48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \
49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \
50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \
51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \
[all …]
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mpc.h35 SRII(MPCC_TOP_GAIN, MPCC, inst),\
36 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
37 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
38 SRII(MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM, inst),\
39 SRII(MPCC_OGAM_RAMA_START_CNTL_G, MPCC_OGAM, inst),\
40 SRII(MPCC_OGAM_RAMA_START_CNTL_R, MPCC_OGAM, inst),\
41 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_B, MPCC_OGAM, inst),\
42 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_G, MPCC_OGAM, inst),\
43 SRII(MPCC_OGAM_RAMA_SLOPE_CNTL_R, MPCC_OGAM, inst),\
44 SRII(MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM, inst),\
[all …]
Ddcn20_dwb.h49 #define SRII(reg_name, block, id)\ macro
Ddcn20_resource.c505 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_mpc.h47 SRII(MPCC_TOP_GAIN, MPCC, inst),\
48 SRII(MPCC_BOT_GAIN_INSIDE, MPCC, inst),\
49 SRII(MPCC_BOT_GAIN_OUTSIDE, MPCC, inst),\
50 SRII(MPCC_MEM_PWR_CTRL, MPCC, inst),\
51 SRII(MPCC_OGAM_LUT_INDEX, MPCC_OGAM, inst),\
52 SRII(MPCC_OGAM_LUT_DATA, MPCC_OGAM, inst), \
53 SRII(MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_OGAM, inst),\
54 SRII(MPCC_GAMUT_REMAP_MODE, MPCC_OGAM, inst),\
55 SRII(MPC_GAMUT_REMAP_C11_C12_A, MPCC_OGAM, inst),\
56 SRII(MPC_GAMUT_REMAP_C33_C34_A, MPCC_OGAM, inst),\
[all …]
Ddcn30_resource.c262 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_mpc.h34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
[all …]
Ddcn10_dwb.h45 #define SRII(reg_name, block, id)\ macro
Ddcn10_resource.c181 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c284 #define SRII(reg_name, block, id)\ macro
763 SRII(PIXEL_RATE_CNTL, OTG, 0), \
764 SRII(PIXEL_RATE_CNTL, OTG, 1),\
765 SRII(PIXEL_RATE_CNTL, OTG, 2),\
766 SRII(PIXEL_RATE_CNTL, OTG, 3),\
767 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
768 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
769 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
770 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c489 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c773 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c519 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c612 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c607 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c541 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c326 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c303 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c307 #define SRII(reg_name, block, id)\ macro
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c338 #define SRII(reg_name, block, id)\ macro