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Searched refs:SR_CLR_SB_ECC_INTR (Results 1 – 1 of 1) sorted by relevance

/drivers/edac/
Dhighbank_l2_edac.c15 #define SR_CLR_SB_ECC_INTR 0x0 macro
30 writel(1, drvdata->base + SR_CLR_SB_ECC_INTR); in highbank_l2_err_handler()