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Searched refs:SSPP_MAX (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_pipe.h11 #define SSPP_MAX (SSPP_CURSOR1 + 1) macro
33 struct drm_plane *hwpipe_to_plane[SSPP_MAX];
Dmdp5_smp.c26 u32 pipe_reqprio_fifo_wm0[SSPP_MAX];
27 u32 pipe_reqprio_fifo_wm1[SSPP_MAX];
28 u32 pipe_reqprio_fifo_wm2[SSPP_MAX];
Dmdp5_kms.h28 struct mdp5_hw_pipe *hwpipes[SSPP_MAX];
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.h53 u8 sspp[SSPP_MAX];
Ddpu_hw_ctl.c40 static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
551 for (i = 0; i < SSPP_MAX; i++) { in dpu_hw_ctl_set_fetch_pipe_active()
Ddpu_hw_mdss.h124 SSPP_MAX enumerator
Ddpu_crtc.c225 DECLARE_BITMAP(fetch_active, SSPP_MAX); in _dpu_crtc_blend_setup_mixer()
938 const struct drm_plane_state *pipe_staged[SSPP_MAX]; in dpu_crtc_atomic_check()
1021 for (i = 1; i < SSPP_MAX; i++) { in dpu_crtc_atomic_check()
Ddpu_hw_sspp.c695 if ((sspp < SSPP_MAX) && catalog && addr && b) { in _sspp_offset()
Ddpu_kms.c84 for (i = SSPP_VIG0; i < SSPP_MAX; i++) in _dpu_danger_signal_status()