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Searched refs:SSPP_VIG2 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
117 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
206 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
458 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
Dmdp5_ctl.c294 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
317 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
445 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
Dmdp5.xml.h79 SSPP_VIG2 = 3, enumerator
553 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); in __offset_PIPE()
Dmdp5_kms.c727 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c140 status->sspp[SSPP_VIG2] = (value >> 8) & 0x3; in dpu_hw_get_danger_status()
237 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_ctl.c153 case SSPP_VIG2: in dpu_hw_ctl_get_bitmask_sspp()
410 case SSPP_VIG2: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_mdss.h112 SSPP_VIG2, enumerator
Ddpu_hw_catalog.c535 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
577 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,