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Searched refs:T (Results 1 – 25 of 84) sorted by relevance

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/drivers/net/wireguard/selftest/
Dcounter.c24 #define T(n, v) do { \ in wg_packet_counter_selftest() macro
34 /* 1 */ T(0, true); in wg_packet_counter_selftest()
35 /* 2 */ T(1, true); in wg_packet_counter_selftest()
36 /* 3 */ T(1, false); in wg_packet_counter_selftest()
37 /* 4 */ T(9, true); in wg_packet_counter_selftest()
38 /* 5 */ T(8, true); in wg_packet_counter_selftest()
39 /* 6 */ T(7, true); in wg_packet_counter_selftest()
40 /* 7 */ T(7, false); in wg_packet_counter_selftest()
41 /* 8 */ T(T_LIM, true); in wg_packet_counter_selftest()
42 /* 9 */ T(T_LIM - 1, true); in wg_packet_counter_selftest()
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/drivers/comedi/drivers/tests/
Dni_routes_test.c310 const struct ni_route_tables *T = &private.routing_tables; in test_ni_route_to_register() local
313 unittest(ni_route_to_register(O(0), O(0), T) < 0, in test_ni_route_to_register()
315 unittest(ni_route_to_register(O(1), O(0), T) == 1, in test_ni_route_to_register()
317 unittest(ni_route_to_register(O(6), O(5), T) == 6, in test_ni_route_to_register()
319 unittest(ni_route_to_register(O(8), O(9), T) == 8, in test_ni_route_to_register()
323 unittest(ni_route_to_register(rgout0_src0, TRIGGER_LINE(0), T) == 0, in test_ni_route_to_register()
325 unittest(ni_route_to_register(rgout0_src0, TRIGGER_LINE(1), T) == 0, in test_ni_route_to_register()
327 unittest(ni_route_to_register(rgout0_src1, TRIGGER_LINE(2), T) == 1, in test_ni_route_to_register()
329 unittest(ni_route_to_register(rgout0_src1, TRIGGER_LINE(3), T) == 1, in test_ni_route_to_register()
332 unittest(ni_route_to_register(brd0_src0, TRIGGER_LINE(4), T) == in test_ni_route_to_register()
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/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv50.c71 #define T(t) cfg->timing_10_##t macro
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
100 T(CWL) << 8 | in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
105 max_t(s8, T(CWL) - 2, 1) << 8 | in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
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Dramgt215.c346 #define T(t) cfg->timing_10_##t macro
362 switch ((!T(CWL)) * ram->base.type) { in gt215_ram_timing_calc()
364 T(CWL) = T(CL) - 1; in gt215_ram_timing_calc()
367 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in gt215_ram_timing_calc()
374 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in gt215_ram_timing_calc()
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in gt215_ram_timing_calc()
376 max_t(u8,T(18), 1) << 16 | in gt215_ram_timing_calc()
377 (T(WTR) + 1 + T(CWL)) << 8 | in gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
379 timing[2] = (T(CWL) - 1) << 24 | in gt215_ram_timing_calc()
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/drivers/gpu/drm/i915/
Di915_params.c30 #define i915_param_named(name, T, perm, desc) \ argument
31 module_param_named(name, i915_modparams.name, T, perm); \
33 #define i915_param_named_unsafe(name, T, perm, desc) \ argument
34 module_param_named_unsafe(name, i915_modparams.name, T, perm); \
38 #define MEMBER(T, member, value, ...) .member = (value), argument
234 #define PRINT(T, x, ...) _print_param(p, #x, #T, &params->x); in i915_params_dump() argument
248 #define DUP(T, x, ...) dup_param(#T, &dest->x); in i915_params_copy() argument
264 #define FREE(T, x, ...) free_param(#T, &params->x); in i915_params_free() argument
Di915_selftest.h89 #define i915_subtests(T, data) \ argument
92 T, ARRAY_SIZE(T), data)
93 #define i915_live_subtests(T, data) ({ \ argument
97 T, ARRAY_SIZE(T), data); \
99 #define intel_gt_live_subtests(T, data) ({ \ argument
103 T, ARRAY_SIZE(T), data); \
Di915_utils.h86 #define add_overflows_t(T, A, B) \ argument
87 __builtin_add_overflow_p((A), (B), (T)0)
89 #define add_overflows_t(T, A, B) ({ \ argument
92 (T)(a + b) < a; \
124 #define overflows_type(x, T) \ argument
125 (sizeof(x) > sizeof(T) && (x) >> BITS_PER_TYPE(T))
194 #define struct_member(T, member) (((T *)0)->member) argument
245 #define u64_to_ptr(T, x) ({ \ argument
247 (T *)(uintptr_t)(x); \
/drivers/ata/
Dlibata-pata-timings.c61 struct ata_timing *q, int T, int UT) in ata_timing_quantize() argument
63 q->setup = EZ(t->setup, T); in ata_timing_quantize()
64 q->act8b = EZ(t->act8b, T); in ata_timing_quantize()
65 q->rec8b = EZ(t->rec8b, T); in ata_timing_quantize()
66 q->cyc8b = EZ(t->cyc8b, T); in ata_timing_quantize()
67 q->active = EZ(t->active, T); in ata_timing_quantize()
68 q->recover = EZ(t->recover, T); in ata_timing_quantize()
69 q->dmack_hold = EZ(t->dmack_hold, T); in ata_timing_quantize()
70 q->cycle = EZ(t->cycle, T); in ata_timing_quantize()
116 struct ata_timing *t, int T, int UT) in ata_timing_compute() argument
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Dpata_imx.c60 u32 T, mode; in pata_imx_set_timing() local
68 T = 1000000000 / clkrate; in pata_imx_set_timing()
69 ata_timing_compute(adev, adev->pio_mode, &timing, T * 1000, 0); in pata_imx_set_timing()
80 writeb(pio_t4[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_4); in pata_imx_set_timing()
81 writeb(pio_t9[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_9); in pata_imx_set_timing()
82 writeb(pio_tA[mode] / T + 1, priv->host_regs + PATA_IMX_ATA_TIME_AX); in pata_imx_set_timing()
Dpata_ali.c211 unsigned long T = 1000000000 / 33333; /* PCI clock based */ in ali_set_piomode() local
213 ata_timing_compute(adev, adev->pio_mode, &t, T, 1); in ali_set_piomode()
216 ata_timing_compute(pair, pair->pio_mode, &p, T, 1); in ali_set_piomode()
219 ata_timing_compute(pair, pair->dma_mode, &p, T, 1); in ali_set_piomode()
246 unsigned long T = 1000000000 / 33333; /* PCI clock based */ in ali_set_dmamode() local
262 ata_timing_compute(adev, adev->dma_mode, &t, T, 1); in ali_set_dmamode()
265 ata_timing_compute(pair, pair->pio_mode, &p, T, 1); in ali_set_dmamode()
268 ata_timing_compute(pair, pair->dma_mode, &p, T, 1); in ali_set_dmamode()
Dpata_amd.c53 int T, UT; in timing_setup() local
57 T = 1000000000 / amd_clock; in timing_setup()
58 UT = T; in timing_setup()
60 UT = T / 2; in timing_setup()
62 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) { in timing_setup()
70 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT); in timing_setup()
73 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT); in timing_setup()
Dpata_via.c252 unsigned long T = 1000000000 / via_clock; in via_do_set_mode() local
253 unsigned long UT = T; in via_do_set_mode()
259 UT = T / 2; break; in via_do_set_mode()
261 UT = T / 3; break; in via_do_set_mode()
263 UT = T / 4; break; in via_do_set_mode()
267 ata_timing_compute(adev, mode, &t, T, UT); in via_do_set_mode()
272 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); in via_do_set_mode()
Dpata_atp867x.c208 int T, UT; in atp867x_set_piomode() local
211 T = 1000000000 / 33333; in atp867x_set_piomode()
212 UT = T / 4; in atp867x_set_piomode()
214 ata_timing_compute(adev, speed, &t, T, UT); in atp867x_set_piomode()
216 ata_timing_compute(peer, peer->pio_mode, &p, T, UT); in atp867x_set_piomode()
/drivers/media/usb/dvb-usb/
DKconfig36 tristate "AVerMedia AverTV DVB-T USB 2.0 (A800)"
42 Say Y here to support the AVerMedia AverTV DVB-T USB 2.0 (A800) receiver.
45 tristate "DiBcom USB DVB-T devices (based on the DiB3000M-B) (see help for device list)"
52 Support for USB 1.1 and 2.0 DVB-T receivers based on reference designs made by
68 tristate "DiBcom USB DVB-T devices (based on the DiB3000M-C/P) (see help for device list)"
73 Support for USB2.0 DVB-T receivers based on reference designs made by
103 USB bridge is also present in devices having the DiB7700 DVB-T-USB
114 tristate "HanfTek UMT-010 DVB-T USB2.0 support"
121 Say Y here to support the HanfTek UMT-010 USB2.0 stick-sized DVB-T receiver.
163 tristate "Uli m920x DVB-T USB2.0 support"
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/drivers/macintosh/
Dtherm_windtunnel.c71 #define T(x,y) (((x)<<8) | (y)*0x100/10 ) macro
78 { 11, T(0,0), 11 }, /* min fan */
79 { 11, T(55,0), 11 },
80 { 6, T(55,3), 11 },
81 { 7, T(56,0), 11 },
82 { 8, T(57,0), 8 },
83 { 7, T(58,3), 7 },
84 { 6, T(58,8), 6 },
85 { 5, T(59,2), 5 },
86 { 4, T(59,6), 4 },
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/drivers/media/usb/dvb-usb-v2/
DKconfig18 tristate "Afatech AF9015 DVB-T USB2.0 support"
31 Say Y here to support the Afatech AF9015 based DVB-T USB2.0 receiver
34 tristate "Afatech AF9035 DVB-T USB2.0 support"
49 tristate "Anysee DVB-T/C USB2.0 support"
71 Say Y here to support the Sigmatek DVB-110 DVB-T USB2.0 receiver.
74 tristate "AzureWave 6007 and clones DVB-T/C USB2.0 support"
83 tristate "Intel CE6230 DVB-T USB2.0 support"
88 Say Y here to support the Intel CE6230 DVB-T USB2.0 receiver
91 tristate "E3C EC168 DVB-T USB2.0 support"
96 Say Y here to support the E3C EC168 DVB-T USB2.0 receiver.
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/drivers/block/drbd/
Ddrbd_state.h37 #define NS(T, S) \ argument
38 ({ union drbd_state mask; mask.i = 0; mask.T = T##_MASK; mask; }), \
39 ({ union drbd_state val; val.i = 0; val.T = (S); val; })
51 #define _NS(D, T, S) \ argument
52 D, ({ union drbd_state __ns; __ns = drbd_read_state(D); __ns.T = (S); __ns; })
/drivers/gpu/drm/selftests/
Ddrm_selftest.h36 #define drm_subtests(T, data) \ argument
37 __drm_subtests(__func__, T, ARRAY_SIZE(T), data)
/drivers/dma-buf/
Dselftest.h25 #define subtests(T, data) \ argument
26 __subtests(__func__, T, ARRAY_SIZE(T), data)
/drivers/mtd/devices/
Dslram.c52 #define T(fmt, args...) printk(KERN_DEBUG fmt, ## args) macro
191 T("slram: Registered device %s from %luKiB to %luKiB\n", name, in register_device()
193 T("slram: Mapped from 0x%p to 0x%p\n", in register_device()
249 T("slram: devname=%s, devstart=0x%lx, devlength=0x%lx\n", in parse_cmdline()
296 T("slram: devname = %s\n", devname); in init_slram()
300 T("slram: devstart = %s\n", devstart); in init_slram()
304 T("slram: devlength = %s\n", devlength); in init_slram()
/drivers/gpu/drm/nouveau/nvkm/subdev/top/
Dga100.c69 #define I_(T,I) do { info->type = (T); info->inst = (I); } while(0) in ga100_top_oneinit() argument
70 #define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0) in ga100_top_oneinit() argument
Dgk104.c73 #define I_(T,I) do { info->type = (T); info->inst = (I); } while(0) in gk104_top_oneinit() argument
74 #define O_(T,I) do { WARN_ON(inst); I_(T, I); } while (0) in gk104_top_oneinit() argument
/drivers/phy/mediatek/
DKconfig6 tristate "MediaTek T-PHY Driver"
12 Say 'Y' here to add support for MediaTek T-PHY driver,
14 SATA, and meanwhile supports two version T-PHY which have
15 different banks layout, the T-PHY with shared banks between
/drivers/media/dvb-frontends/
DKconfig88 Micronas DRX-K DVB-C/T demodulator.
107 A DVB-C/T demodulator.
323 comment "DVB-T (terrestrial) frontends"
331 A DVB-T tuner module. Say Y when you want to support this frontend.
343 A DVB-T tuner module. Say Y when you want to support this frontend.
350 A DVB-T tuner module. Say Y when you want to support this frontend.
357 A DVB-T tuner module. Say Y when you want to support this frontend.
364 A DVB-T tuner module. Say Y when you want to support this frontend.
375 A DVB-T tuner module. Say Y when you want to support this frontend.
382 A DVB-T tuner module. Say Y when you want to support this frontend.
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/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_debugfs.c2678 #define T(s, v) S3("u", s, tx[i].v) in sge_qinfo_show() macro
2694 T("TxQ ID:", q.cntxt_id); in sge_qinfo_show()
2695 T("TxQ size:", q.size); in sge_qinfo_show()
2696 T("TxQ inuse:", q.in_use); in sge_qinfo_show()
2697 T("TxQ CIDX:", q.cidx); in sge_qinfo_show()
2698 T("TxQ PIDX:", q.pidx); in sge_qinfo_show()
2700 T("DCB Prio:", dcb_prio); in sge_qinfo_show()
2817 T("TxQ ID:", q.cntxt_id); in sge_qinfo_show()
2818 T("TxQ size:", q.size); in sge_qinfo_show()
2819 T("TxQ inuse:", q.in_use); in sge_qinfo_show()
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