1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Aquantia PHY
4 *
5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
6 *
7 * Copyright 2015 Freescale Semiconductor, Inc.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/bitfield.h>
14 #include <linux/phy.h>
15
16 #include "aquantia.h"
17
18 #define PHY_ID_AQ1202 0x03a1b445
19 #define PHY_ID_AQ2104 0x03a1b460
20 #define PHY_ID_AQR105 0x03a1b4a2
21 #define PHY_ID_AQR106 0x03a1b4d0
22 #define PHY_ID_AQR107 0x03a1b4e0
23 #define PHY_ID_AQCS109 0x03a1b5c2
24 #define PHY_ID_AQR405 0x03a1b4b0
25
26 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
27 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
33
34 #define MDIO_AN_VEND_PROV 0xc400
35 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
36 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
37 #define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
38 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
39 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
40 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
41 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
42
43 #define MDIO_AN_TX_VEND_STATUS1 0xc800
44 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
45 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0
46 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
47 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
48 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
49 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
50 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
51 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
52
53 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
54 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
55
56 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
57 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
58
59 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401
60 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
61
62 #define MDIO_AN_RX_LP_STAT1 0xe820
63 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
64 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
65 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
66 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
67 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
68
69 #define MDIO_AN_RX_LP_STAT4 0xe823
70 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
71 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
72
73 #define MDIO_AN_RX_VEND_STAT3 0xe832
74 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
75
76 /* MDIO_MMD_C22EXT */
77 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
78 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
79 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
80 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
81 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
82 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
83 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
84 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
85 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
86 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
87
88 /* Vendor specific 1, MDIO_MMD_VEND1 */
89 #define VEND1_GLOBAL_FW_ID 0x0020
90 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
91 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
92
93 #define VEND1_GLOBAL_GEN_STAT2 0xc831
94 #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
95
96 #define VEND1_GLOBAL_RSVD_STAT1 0xc885
97 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
98 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
99
100 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d
101 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
102 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
103
104 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
105 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
106
107 #define VEND1_GLOBAL_INT_STD_MASK 0xff00
108 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
109 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
110 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
111 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
112 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
113 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
114 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
115 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
116 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
117 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
118 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
119
120 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01
121 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
122 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
123 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
124 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
125 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
126 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
127 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
128 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
129
130 /* Sleep and timeout for checking if the Processor-Intensive
131 * MDIO operation is finished
132 */
133 #define AQR107_OP_IN_PROG_SLEEP 1000
134 #define AQR107_OP_IN_PROG_TIMEOUT 100000
135
136 struct aqr107_hw_stat {
137 const char *name;
138 int reg;
139 int size;
140 };
141
142 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
143 static const struct aqr107_hw_stat aqr107_hw_stats[] = {
144 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
145 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
146 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
147 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
148 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
149 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
150 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
151 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
152 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
153 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
154 };
155 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
156
157 struct aqr107_priv {
158 u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
159 };
160
aqr107_get_sset_count(struct phy_device * phydev)161 static int aqr107_get_sset_count(struct phy_device *phydev)
162 {
163 return AQR107_SGMII_STAT_SZ;
164 }
165
aqr107_get_strings(struct phy_device * phydev,u8 * data)166 static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
167 {
168 int i;
169
170 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
171 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
172 ETH_GSTRING_LEN);
173 }
174
aqr107_get_stat(struct phy_device * phydev,int index)175 static u64 aqr107_get_stat(struct phy_device *phydev, int index)
176 {
177 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
178 int len_l = min(stat->size, 16);
179 int len_h = stat->size - len_l;
180 u64 ret;
181 int val;
182
183 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
184 if (val < 0)
185 return U64_MAX;
186
187 ret = val & GENMASK(len_l - 1, 0);
188 if (len_h) {
189 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
190 if (val < 0)
191 return U64_MAX;
192
193 ret += (val & GENMASK(len_h - 1, 0)) << 16;
194 }
195
196 return ret;
197 }
198
aqr107_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)199 static void aqr107_get_stats(struct phy_device *phydev,
200 struct ethtool_stats *stats, u64 *data)
201 {
202 struct aqr107_priv *priv = phydev->priv;
203 u64 val;
204 int i;
205
206 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
207 val = aqr107_get_stat(phydev, i);
208 if (val == U64_MAX)
209 phydev_err(phydev, "Reading HW Statistics failed for %s\n",
210 aqr107_hw_stats[i].name);
211 else
212 priv->sgmii_stats[i] += val;
213
214 data[i] = priv->sgmii_stats[i];
215 }
216 }
217
aqr_config_aneg(struct phy_device * phydev)218 static int aqr_config_aneg(struct phy_device *phydev)
219 {
220 bool changed = false;
221 u16 reg;
222 int ret;
223
224 if (phydev->autoneg == AUTONEG_DISABLE)
225 return genphy_c45_pma_setup_forced(phydev);
226
227 ret = genphy_c45_an_config_aneg(phydev);
228 if (ret < 0)
229 return ret;
230 if (ret > 0)
231 changed = true;
232
233 /* Clause 45 has no standardized support for 1000BaseT, therefore
234 * use vendor registers for this mode.
235 */
236 reg = 0;
237 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
238 phydev->advertising))
239 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
240
241 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
242 phydev->advertising))
243 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
244
245 /* Handle the case when the 2.5G and 5G speeds are not advertised */
246 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
247 phydev->advertising))
248 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
249
250 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
251 phydev->advertising))
252 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
253
254 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
255 MDIO_AN_VEND_PROV_1000BASET_HALF |
256 MDIO_AN_VEND_PROV_1000BASET_FULL |
257 MDIO_AN_VEND_PROV_2500BASET_FULL |
258 MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
259 if (ret < 0)
260 return ret;
261 if (ret > 0)
262 changed = true;
263
264 return genphy_c45_check_and_restart_aneg(phydev, changed);
265 }
266
aqr_config_intr(struct phy_device * phydev)267 static int aqr_config_intr(struct phy_device *phydev)
268 {
269 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
270 int err;
271
272 if (en) {
273 /* Clear any pending interrupts before enabling them */
274 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
275 if (err < 0)
276 return err;
277 }
278
279 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
280 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
281 if (err < 0)
282 return err;
283
284 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
285 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
286 if (err < 0)
287 return err;
288
289 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
290 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
291 VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
292 if (err < 0)
293 return err;
294
295 if (!en) {
296 /* Clear any pending interrupts after we have disabled them */
297 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
298 if (err < 0)
299 return err;
300 }
301
302 return 0;
303 }
304
aqr_handle_interrupt(struct phy_device * phydev)305 static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
306 {
307 int irq_status;
308
309 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
310 MDIO_AN_TX_VEND_INT_STATUS2);
311 if (irq_status < 0) {
312 phy_error(phydev);
313 return IRQ_NONE;
314 }
315
316 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
317 return IRQ_NONE;
318
319 phy_trigger_machine(phydev);
320
321 return IRQ_HANDLED;
322 }
323
aqr_read_status(struct phy_device * phydev)324 static int aqr_read_status(struct phy_device *phydev)
325 {
326 int val;
327
328 if (phydev->autoneg == AUTONEG_ENABLE) {
329 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
330 if (val < 0)
331 return val;
332
333 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
334 phydev->lp_advertising,
335 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
336 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
337 phydev->lp_advertising,
338 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
339 }
340
341 return genphy_c45_read_status(phydev);
342 }
343
aqr107_read_rate(struct phy_device * phydev)344 static int aqr107_read_rate(struct phy_device *phydev)
345 {
346 int val;
347
348 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
349 if (val < 0)
350 return val;
351
352 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
353 case MDIO_AN_TX_VEND_STATUS1_10BASET:
354 phydev->speed = SPEED_10;
355 break;
356 case MDIO_AN_TX_VEND_STATUS1_100BASETX:
357 phydev->speed = SPEED_100;
358 break;
359 case MDIO_AN_TX_VEND_STATUS1_1000BASET:
360 phydev->speed = SPEED_1000;
361 break;
362 case MDIO_AN_TX_VEND_STATUS1_2500BASET:
363 phydev->speed = SPEED_2500;
364 break;
365 case MDIO_AN_TX_VEND_STATUS1_5000BASET:
366 phydev->speed = SPEED_5000;
367 break;
368 case MDIO_AN_TX_VEND_STATUS1_10GBASET:
369 phydev->speed = SPEED_10000;
370 break;
371 default:
372 phydev->speed = SPEED_UNKNOWN;
373 break;
374 }
375
376 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
377 phydev->duplex = DUPLEX_FULL;
378 else
379 phydev->duplex = DUPLEX_HALF;
380
381 return 0;
382 }
383
aqr107_read_status(struct phy_device * phydev)384 static int aqr107_read_status(struct phy_device *phydev)
385 {
386 int val, ret;
387
388 ret = aqr_read_status(phydev);
389 if (ret)
390 return ret;
391
392 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
393 return 0;
394
395 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
396 if (val < 0)
397 return val;
398
399 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
400 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
401 phydev->interface = PHY_INTERFACE_MODE_10GKR;
402 break;
403 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
404 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
405 break;
406 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
407 phydev->interface = PHY_INTERFACE_MODE_USXGMII;
408 break;
409 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
410 phydev->interface = PHY_INTERFACE_MODE_SGMII;
411 break;
412 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
413 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
414 break;
415 default:
416 phydev->interface = PHY_INTERFACE_MODE_NA;
417 break;
418 }
419
420 /* Read possibly downshifted rate from vendor register */
421 return aqr107_read_rate(phydev);
422 }
423
aqr107_get_downshift(struct phy_device * phydev,u8 * data)424 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
425 {
426 int val, cnt, enable;
427
428 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
429 if (val < 0)
430 return val;
431
432 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
433 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
434
435 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
436
437 return 0;
438 }
439
aqr107_set_downshift(struct phy_device * phydev,u8 cnt)440 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
441 {
442 int val = 0;
443
444 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
445 return -E2BIG;
446
447 if (cnt != DOWNSHIFT_DEV_DISABLE) {
448 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
449 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
450 }
451
452 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
453 MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
454 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
455 }
456
aqr107_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)457 static int aqr107_get_tunable(struct phy_device *phydev,
458 struct ethtool_tunable *tuna, void *data)
459 {
460 switch (tuna->id) {
461 case ETHTOOL_PHY_DOWNSHIFT:
462 return aqr107_get_downshift(phydev, data);
463 default:
464 return -EOPNOTSUPP;
465 }
466 }
467
aqr107_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)468 static int aqr107_set_tunable(struct phy_device *phydev,
469 struct ethtool_tunable *tuna, const void *data)
470 {
471 switch (tuna->id) {
472 case ETHTOOL_PHY_DOWNSHIFT:
473 return aqr107_set_downshift(phydev, *(const u8 *)data);
474 default:
475 return -EOPNOTSUPP;
476 }
477 }
478
479 /* If we configure settings whilst firmware is still initializing the chip,
480 * then these settings may be overwritten. Therefore make sure chip
481 * initialization has completed. Use presence of the firmware ID as
482 * indicator for initialization having completed.
483 * The chip also provides a "reset completed" bit, but it's cleared after
484 * read. Therefore function would time out if called again.
485 */
aqr107_wait_reset_complete(struct phy_device * phydev)486 static int aqr107_wait_reset_complete(struct phy_device *phydev)
487 {
488 int val;
489
490 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
491 VEND1_GLOBAL_FW_ID, val, val != 0,
492 20000, 2000000, false);
493 }
494
aqr107_chip_info(struct phy_device * phydev)495 static void aqr107_chip_info(struct phy_device *phydev)
496 {
497 u8 fw_major, fw_minor, build_id, prov_id;
498 int val;
499
500 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
501 if (val < 0)
502 return;
503
504 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
505 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
506
507 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
508 if (val < 0)
509 return;
510
511 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
512 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
513
514 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
515 fw_major, fw_minor, build_id, prov_id);
516 }
517
aqr107_config_init(struct phy_device * phydev)518 static int aqr107_config_init(struct phy_device *phydev)
519 {
520 int ret;
521
522 /* Check that the PHY interface type is compatible */
523 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
524 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
525 phydev->interface != PHY_INTERFACE_MODE_XGMII &&
526 phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
527 phydev->interface != PHY_INTERFACE_MODE_10GKR &&
528 phydev->interface != PHY_INTERFACE_MODE_10GBASER)
529 return -ENODEV;
530
531 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
532 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
533
534 ret = aqr107_wait_reset_complete(phydev);
535 if (!ret)
536 aqr107_chip_info(phydev);
537
538 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
539 }
540
aqcs109_config_init(struct phy_device * phydev)541 static int aqcs109_config_init(struct phy_device *phydev)
542 {
543 int ret;
544
545 /* Check that the PHY interface type is compatible */
546 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
547 phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
548 return -ENODEV;
549
550 ret = aqr107_wait_reset_complete(phydev);
551 if (!ret)
552 aqr107_chip_info(phydev);
553
554 /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
555 * PMA speed ability bits are the same for all members of the family,
556 * AQCS109 however supports speeds up to 2.5G only.
557 */
558 ret = phy_set_max_speed(phydev, SPEED_2500);
559 if (ret)
560 return ret;
561
562 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
563 }
564
aqr107_link_change_notify(struct phy_device * phydev)565 static void aqr107_link_change_notify(struct phy_device *phydev)
566 {
567 u8 fw_major, fw_minor;
568 bool downshift, short_reach, afr;
569 int mode, val;
570
571 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
572 return;
573
574 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
575 /* call failed or link partner is no Aquantia PHY */
576 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
577 return;
578
579 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
580 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
581
582 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
583 if (val < 0)
584 return;
585
586 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
587 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
588
589 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
590 if (val < 0)
591 return;
592
593 afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
594
595 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
596 fw_major, fw_minor,
597 short_reach ? ", short reach mode" : "",
598 downshift ? ", fast-retrain downshift advertised" : "",
599 afr ? ", fast reframe advertised" : "");
600
601 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
602 if (val < 0)
603 return;
604
605 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
606 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
607 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
608 }
609
aqr107_wait_processor_intensive_op(struct phy_device * phydev)610 static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
611 {
612 int val, err;
613
614 /* The datasheet notes to wait at least 1ms after issuing a
615 * processor intensive operation before checking.
616 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
617 * because that just determines the maximum time slept, not the minimum.
618 */
619 usleep_range(1000, 5000);
620
621 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
622 VEND1_GLOBAL_GEN_STAT2, val,
623 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
624 AQR107_OP_IN_PROG_SLEEP,
625 AQR107_OP_IN_PROG_TIMEOUT, false);
626 if (err) {
627 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
628 return err;
629 }
630
631 return 0;
632 }
633
aqr107_suspend(struct phy_device * phydev)634 static int aqr107_suspend(struct phy_device *phydev)
635 {
636 int err;
637
638 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
639 MDIO_CTRL1_LPOWER);
640 if (err)
641 return err;
642
643 return aqr107_wait_processor_intensive_op(phydev);
644 }
645
aqr107_resume(struct phy_device * phydev)646 static int aqr107_resume(struct phy_device *phydev)
647 {
648 int err;
649
650 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
651 MDIO_CTRL1_LPOWER);
652 if (err)
653 return err;
654
655 return aqr107_wait_processor_intensive_op(phydev);
656 }
657
aqr107_probe(struct phy_device * phydev)658 static int aqr107_probe(struct phy_device *phydev)
659 {
660 phydev->priv = devm_kzalloc(&phydev->mdio.dev,
661 sizeof(struct aqr107_priv), GFP_KERNEL);
662 if (!phydev->priv)
663 return -ENOMEM;
664
665 return aqr_hwmon_probe(phydev);
666 }
667
668 static struct phy_driver aqr_driver[] = {
669 {
670 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
671 .name = "Aquantia AQ1202",
672 .config_aneg = aqr_config_aneg,
673 .config_intr = aqr_config_intr,
674 .handle_interrupt = aqr_handle_interrupt,
675 .read_status = aqr_read_status,
676 },
677 {
678 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
679 .name = "Aquantia AQ2104",
680 .config_aneg = aqr_config_aneg,
681 .config_intr = aqr_config_intr,
682 .handle_interrupt = aqr_handle_interrupt,
683 .read_status = aqr_read_status,
684 },
685 {
686 PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
687 .name = "Aquantia AQR105",
688 .config_aneg = aqr_config_aneg,
689 .config_intr = aqr_config_intr,
690 .handle_interrupt = aqr_handle_interrupt,
691 .read_status = aqr_read_status,
692 .suspend = aqr107_suspend,
693 .resume = aqr107_resume,
694 },
695 {
696 PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
697 .name = "Aquantia AQR106",
698 .config_aneg = aqr_config_aneg,
699 .config_intr = aqr_config_intr,
700 .handle_interrupt = aqr_handle_interrupt,
701 .read_status = aqr_read_status,
702 },
703 {
704 PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
705 .name = "Aquantia AQR107",
706 .probe = aqr107_probe,
707 .config_init = aqr107_config_init,
708 .config_aneg = aqr_config_aneg,
709 .config_intr = aqr_config_intr,
710 .handle_interrupt = aqr_handle_interrupt,
711 .read_status = aqr107_read_status,
712 .get_tunable = aqr107_get_tunable,
713 .set_tunable = aqr107_set_tunable,
714 .suspend = aqr107_suspend,
715 .resume = aqr107_resume,
716 .get_sset_count = aqr107_get_sset_count,
717 .get_strings = aqr107_get_strings,
718 .get_stats = aqr107_get_stats,
719 .link_change_notify = aqr107_link_change_notify,
720 },
721 {
722 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
723 .name = "Aquantia AQCS109",
724 .probe = aqr107_probe,
725 .config_init = aqcs109_config_init,
726 .config_aneg = aqr_config_aneg,
727 .config_intr = aqr_config_intr,
728 .handle_interrupt = aqr_handle_interrupt,
729 .read_status = aqr107_read_status,
730 .get_tunable = aqr107_get_tunable,
731 .set_tunable = aqr107_set_tunable,
732 .suspend = aqr107_suspend,
733 .resume = aqr107_resume,
734 .get_sset_count = aqr107_get_sset_count,
735 .get_strings = aqr107_get_strings,
736 .get_stats = aqr107_get_stats,
737 .link_change_notify = aqr107_link_change_notify,
738 },
739 {
740 PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
741 .name = "Aquantia AQR405",
742 .config_aneg = aqr_config_aneg,
743 .config_intr = aqr_config_intr,
744 .handle_interrupt = aqr_handle_interrupt,
745 .read_status = aqr_read_status,
746 },
747 };
748
749 module_phy_driver(aqr_driver);
750
751 static struct mdio_device_id __maybe_unused aqr_tbl[] = {
752 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
753 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
754 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
755 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
756 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
757 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
758 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
759 { }
760 };
761
762 MODULE_DEVICE_TABLE(mdio, aqr_tbl);
763
764 MODULE_DESCRIPTION("Aquantia PHY driver");
765 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
766 MODULE_LICENSE("GPL v2");
767