Searched refs:WM_D (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 149 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true; in dcn3_build_wm_range_table()
150 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()
151 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2; in dcn3_build_wm_range_table()
152 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4; in dcn3_build_wm_range_table()
153 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL; in dcn3_build_wm_range_table()
154 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
155 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()
156 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_build_wm_range_table()
157 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF; in dcn3_build_wm_range_table()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 645 .wm_inst = WM_D,
682 .wm_inst = WM_D,
719 .wm_inst = WM_D,
756 .wm_inst = WM_D,
793 .wm_inst = WM_D,
830 .wm_inst = WM_D,
919 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; in rn_clk_mgr_helper_populate_bw_params()
920 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; in rn_clk_mgr_helper_populate_bw_params()
921 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; in rn_clk_mgr_helper_populate_bw_params()
922 bw_params->wm_table.entries[WM_D].valid = true; in rn_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 569 .wm_inst = WM_D,
606 .wm_inst = WM_D,
686 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY; in vg_clk_mgr_helper_populate_bw_params()
687 bw_params->wm_table.entries[WM_D].wm_inst = WM_D; in vg_clk_mgr_helper_populate_bw_params()
688 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING; in vg_clk_mgr_helper_populate_bw_params()
689 bw_params->wm_table.entries[WM_D].valid = true; in vg_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 40 #define WM_D 3 macro
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 359 .wm_inst = WM_D,
396 .wm_inst = WM_D,
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1733 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) { in dcn31_calculate_wm_and_dlg_fp()
1734 …ram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_l… in dcn31_calculate_wm_and_dlg_fp()
1735 ….sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter… in dcn31_calculate_wm_and_dlg_fp()
1736 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_in… in dcn31_calculate_wm_and_dlg_fp()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 46 #define WM_D 3 macro
1605 ranges.reader_wm_sets[3].wm_inst = WM_D; in dcn_bw_notify_pplib_of_wm_ranges()
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1677 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1156 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
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