Searched refs:WritebackHTaps (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_mode_vba_30.h | 36 unsigned int WritebackHTaps,
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| D | display_mode_vba_30.c | 1960 v->WritebackHTaps[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3335 unsigned int WritebackHTaps, in dml30_CalculateWriteBackDISPCLK() argument
3344 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio; in dml30_CalculateWriteBackDISPCLK()
3823 || v->WritebackHTaps[k] in dml30_ModeSupportAndSystemConfigurationFull()
3828 > v->WritebackHTaps[k] in dml30_ModeSupportAndSystemConfigurationFull()
3831 || (v->WritebackHTaps[k] > 2.0 in dml30_ModeSupportAndSystemConfigurationFull()
3832 && ((v->WritebackHTaps[k] % 2) in dml30_ModeSupportAndSystemConfigurationFull()
3852 v->WritebackHTaps[k], in dml30_ModeSupportAndSystemConfigurationFull()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_mode_vba_31.h | 36 unsigned int WritebackHTaps,
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| D | display_mode_vba_31.c | 2094 v->WritebackHTaps[k],
3509 unsigned int WritebackHTaps, argument
3518 DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
3958 || v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
3960 || v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
3961 || (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
3981 v->WritebackHTaps[k],
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_vba.h | 852 unsigned int WritebackHTaps[DC__NUM_DPP__MAX]; member
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| D | display_mode_vba.c | 523 mode_lib->vba.WritebackHTaps[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
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