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Searched refs:__offset_DSPP (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h1270 static inline uint32_t __offset_DSPP(uint32_t idx) in __offset_DSPP() function
1280 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP()
1282 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } in REG_MDP5_DSPP_OP_MODE()
1299 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);… in REG_MDP5_DSPP_PCC_BASE()
1301 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(… in REG_MDP5_DSPP_DITHER_DEPTH()
1303 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP in REG_MDP5_DSPP_HIST_CTL_BASE()
1305 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP in REG_MDP5_DSPP_HIST_LUT_BASE()
1307 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP in REG_MDP5_DSPP_HIST_LUT_SWAP()
1309 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } in REG_MDP5_DSPP_PA_BASE()
1311 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0… in REG_MDP5_DSPP_GAMUT_BASE()
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