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Searched refs:__offset_INTF (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h1755 static inline uint32_t __offset_INTF(uint32_t idx) in __offset_INTF() function
1766 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF()
1768 …ine uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } in REG_MDP5_INTF_TIMING_ENGINE_EN()
1770 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } in REG_MDP5_INTF_CONFIG()
1772 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)… in REG_MDP5_INTF_HSYNC_CTL()
1786 …line uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1788 …line uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1790 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(… in REG_MDP5_INTF_VSYNC_LEN_F0()
1792 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(… in REG_MDP5_INTF_VSYNC_LEN_F1()
1794 …ne uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); } in REG_MDP5_INTF_DISPLAY_VSTART_F0()
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