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Searched refs:_idx (Results 1 – 25 of 40) sorted by relevance

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/drivers/net/ethernet/intel/ice/
Dice_ptp.h150 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) argument
151 #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) argument
152 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) argument
153 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) argument
154 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) argument
155 #define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16)) argument
156 #define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16)) argument
/drivers/clk/uniphier/
Dclk-uniphier.h69 #define UNIPHIER_CLK_CPUGEAR(_name, _idx, _regbase, _mask, \ argument
74 .idx = (_idx), \
83 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \ argument
87 .idx = (_idx), \
95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
99 .idx = (_idx), \
Dclk-uniphier-mio.c21 #define UNIPHIER_MIO_CLK_SD(_idx, ch) \ argument
61 UNIPHIER_CLK_GATE("sd" #ch, (_idx), "sd" #ch "-sel", 0x20 + 0x200 * (ch), 8)
/drivers/usb/gadget/udc/
Dpxa27x_udc.h263 #define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ argument
266 .name = "ep" #_idx, \
267 .idx = _idx, .enabled = 0, \
272 #define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \ argument
273 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
275 #define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \ argument
276 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
278 #define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \ argument
279 PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
/drivers/net/wireless/mediatek/mt7601u/
Dregs.h592 #define MT_SKEY_0(_bss, _idx) \ argument
593 (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32)
594 #define MT_SKEY_1(_bss, _idx) \ argument
595 (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32)
596 #define MT_SKEY(_bss, _idx) \ argument
597 ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))
608 #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1))) argument
Dinit.c465 #define CHAN2G(_idx, _freq) { \ argument
468 .hw_value = (_idx), \
489 #define CCK_RATE(_idx, _rate) { \ argument
492 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
493 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
496 #define OFDM_RATE(_idx, _rate) { \ argument
498 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
499 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
/drivers/net/wireless/mediatek/mt76/
Dmt76x02_regs.h666 #define MT_SKEY_0(_bss, _idx) (MT_SKEY_BASE_0 + (4 * (_bss) + (_idx)) * 32) argument
667 #define MT_SKEY_1(_bss, _idx) (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + (_idx)) * 32) argument
668 #define MT_SKEY(_bss, _idx) (((_bss) & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx)) argument
676 #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * ((_bss) & 1))) argument
Dmt76.h759 #define CCK_RATE(_idx, _rate) { \ argument
762 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
763 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \
766 #define OFDM_RATE(_idx, _rate) { \ argument
768 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
769 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \
Dmt76x02_util.c10 #define MT76x02_CCK_RATE(_idx, _rate) { \ argument
13 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \
14 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + (_idx)), \
/drivers/net/wireless/ath/ath9k/
Dcommon-init.c21 #define CHAN2G(_freq, _idx) { \ argument
24 .hw_value = (_idx), \
28 #define CHAN5G(_freq, _idx) { \ argument
31 .hw_value = (_idx), \
/drivers/clk/nxp/
Dclk-lpc32xx.c189 #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \ argument
190 [CLK_PREFIX(_idx)] = { \
1083 #define LPC32XX_DEFINE_FIXED(_idx, _rate) \ argument
1084 [CLK_PREFIX(_idx)] = { \
1093 #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \ argument
1094 [CLK_PREFIX(_idx)] = { \
1109 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ argument
1110 [CLK_PREFIX(_idx)] = { \
1130 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ argument
1131 [CLK_PREFIX(_idx)] = { \
[all …]
/drivers/clk/tegra/
Dclk-tegra-periph.c136 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
143 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
150 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
157 _parents##_idx, 0, _lock)
163 _parents##_idx, 0, NULL)
170 _clk_id, _parents##_idx, 0, NULL)
177 _clk_id, _parents##_idx, flags, NULL)
184 _clk_id, _parents##_idx, 0, NULL)
191 _parents##_idx, 0, NULL)
198 _parents##_idx, 0, NULL)
[all …]
/drivers/clk/renesas/
Dr9a06g032-clocks.c64 #define D_GATE(_idx, _n, _src, ...) \ argument
65 { .type = K_GATE, .index = R9A06G032_##_idx, \
68 #define D_MODULE(_idx, _n, _src, ...) \ argument
69 { .type = K_GATE, .index = R9A06G032_##_idx, \
72 #define D_ROOT(_idx, _n, _mul, _div) \ argument
73 { .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
75 #define D_FFC(_idx, _n, _src, _div) \ argument
76 { .type = K_FFC, .index = R9A06G032_##_idx, \
79 #define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \ argument
80 { .type = K_DIV, .index = R9A06G032_##_idx, \
[all …]
/drivers/iio/adc/
Dmt6360-adc.c226 #define MT6360_ADC_CHAN(_idx, _type) { \ argument
228 .channel = MT6360_CHAN_##_idx, \
229 .scan_index = MT6360_CHAN_##_idx, \
230 .datasheet_name = #_idx, \
Dvf610_adc.c503 #define VF610_ADC_CHAN(_idx, _chan_type) { \ argument
506 .channel = (_idx), \
511 .scan_index = (_idx), \
519 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \ argument
521 .channel = (_idx), \
523 .scan_index = (_idx), \
Dlpc18xx_adc.c51 #define LPC18XX_ADC_CHAN(_idx) { \ argument
54 .channel = _idx, \
Daspeed_adc.c61 #define ASPEED_CHAN(_idx, _data_reg_addr) { \ argument
64 .channel = (_idx), \
Drcar-gyroadc.c124 #define RCAR_GYROADC_CHAN(_idx) { \ argument
127 .channel = (_idx), \
Dimx7d_adc.c141 #define IMX7D_ADC_CHAN(_idx) { \ argument
144 .channel = (_idx), \
/drivers/regulator/
Dmax77826-regulator.c136 #define MAX77826_BUCK(_idx, _id, _ops) \ argument
147 .enable_mask = BIT(_idx * 2 + 1), \
148 .vsel_reg = MAX77826_REG_BUCK_VOUT + _idx * 2, \
/drivers/spi/
Dspi-dw.h114 #define SPI_GET_BYTE(_val, _idx) \ argument
115 ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
/drivers/iio/chemical/
Datlas-sensor.c139 #define ATLAS_CONCENTRATION_CHANNEL(_idx, _addr) \ argument
143 .channel = _idx, \
147 .scan_index = _idx + 1, \
/drivers/misc/vmw_vmci/
Dvmci_doorbell.c27 #define VMCI_DOORBELL_HASH(_idx) hash_32(_idx, VMCI_DOORBELL_INDEX_BITS) argument
/drivers/phy/mscc/
Dphy-ocelot-serdes.c345 #define SERDES_MUX(_idx, _port, _mode, _submode, _mask, _mux) { \ argument
346 .idx = _idx, \
/drivers/net/wireless/mediatek/mt76/mt7915/
Dtestmode.c28 #define REG_BAND_IDX(_reg, _idx) \ argument
29 { .band[0] = MT_##_reg(0, _idx), .band[1] = MT_##_reg(1, _idx) }

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