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Searched refs:bank_reg (Results 1 – 7 of 7) sorted by relevance

/drivers/gpio/
Dgpio-aspeed-sgpio.c103 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() function
179 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
198 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
199 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
278 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
297 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
360 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
365 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
370 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
395 reg = ioread32(bank_reg(data, bank, reg_irq_status)); in aspeed_sgpio_irq_handler()
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Dgpio-aspeed.c208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() function
309 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); in aspeed_gpio_change_cmd_source()
310 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); in aspeed_gpio_change_cmd_source()
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
397 addr = bank_reg(gpio, bank, reg_val); in __aspeed_gpio_set()
430 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_in()
458 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_out()
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
540 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_gpio_irq_ack()
[all …]
/drivers/i2c/
Di2c-stub.c46 static u8 bank_reg[MAX_CHIPS]; variable
47 module_param_array(bank_reg, byte, NULL, S_IRUGO);
48 MODULE_PARM_DESC(bank_reg, "Bank register");
76 u8 bank_reg; member
176 if (chip->bank_words && command == chip->bank_reg) { in stub_xfer()
320 chip->bank_reg = bank_reg[i]; in i2c_stub_allocate_banks()
/drivers/clk/qcom/
Dclk-rcg.c73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_get_parent()
213 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
253 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, in configure_bank()
280 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
284 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); in configure_bank()
300 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_set_parent()
376 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_recalc_rate()
452 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_determine_rate()
Dclk-rcg.h113 u32 bank_reg; member
Dgcc-ipq806x.c2300 .bank_reg = 0x3ca0,
2372 .bank_reg = 0x3ca0,
2444 .bank_reg = 0x3ce0,
2516 .bank_reg = 0x3d00,
2592 .bank_reg = 0x3dc0,
2654 .bank_reg = 0x3d20,
2707 .bank_reg = 0x3d40,
Dmmcc-msm8960.c806 .bank_reg = 0x0060,
866 .bank_reg = 0x0074,
967 .bank_reg = 0x0080,
1045 .bank_reg = 0x0178,
1252 .bank_reg = 0x00c0,
1359 .bank_reg = 0x00e8,
1585 .bank_reg = 0x00f8,