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Searched refs:base_addr (Results 1 – 25 of 356) sorted by relevance

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/drivers/staging/netlogic/
Dxlr_net.c45 static inline void xlr_reg_update(u32 *base_addr, u32 off, u32 val, u32 mask) in xlr_reg_update() argument
49 tmp = xlr_nae_rdreg(base_addr, off); in xlr_reg_update()
50 xlr_nae_wreg(base_addr, off, (tmp & ~mask) | (val & mask)); in xlr_reg_update()
268 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0, in xlr_hw_set_mac_addr()
271 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR0 + 1, in xlr_hw_set_mac_addr()
274 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2, 0xffffffff); in xlr_hw_set_mac_addr()
275 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK2 + 1, 0xffffffff); in xlr_hw_set_mac_addr()
276 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3, 0xffffffff); in xlr_hw_set_mac_addr()
277 xlr_nae_wreg(priv->base_addr, R_MAC_ADDR_MASK3 + 1, 0xffffffff); in xlr_hw_set_mac_addr()
279 xlr_nae_wreg(priv->base_addr, R_MAC_FILTER_CONFIG, in xlr_hw_set_mac_addr()
[all …]
/drivers/irqchip/
Dirq-ftintc010.c27 #define FT010_IRQ_SOURCE(base_addr) (base_addr + 0x00) argument
28 #define FT010_IRQ_MASK(base_addr) (base_addr + 0x04) argument
29 #define FT010_IRQ_CLEAR(base_addr) (base_addr + 0x08) argument
31 #define FT010_IRQ_MODE(base_addr) (base_addr + 0x0C) argument
33 #define FT010_IRQ_POLARITY(base_addr) (base_addr + 0x10) argument
34 #define FT010_IRQ_STATUS(base_addr) (base_addr + 0x14) argument
35 #define FT010_FIQ_SOURCE(base_addr) (base_addr + 0x20) argument
36 #define FT010_FIQ_MASK(base_addr) (base_addr + 0x24) argument
37 #define FT010_FIQ_CLEAR(base_addr) (base_addr + 0x28) argument
38 #define FT010_FIQ_MODE(base_addr) (base_addr + 0x2C) argument
[all …]
/drivers/char/ipmi/
Dipmi_dmi.c35 static void __init dmi_add_platform_ipmi(unsigned long base_addr, in dmi_add_platform_ipmi() argument
70 p.addr = base_addr; in dmi_add_platform_ipmi()
83 info->addr = base_addr; in dmi_add_platform_ipmi()
101 unsigned long base_addr) in ipmi_dmi_get_slave_addr() argument
108 info->addr == base_addr) in ipmi_dmi_get_slave_addr()
130 unsigned long base_addr; in dmi_decode_ipmi() local
142 memcpy(&base_addr, data + DMI_IPMI_ADDR, sizeof(unsigned long)); in dmi_decode_ipmi()
143 if (!base_addr) { in dmi_decode_ipmi()
150 base_addr = data[DMI_IPMI_ADDR] >> 1; in dmi_decode_ipmi()
151 if (base_addr == 0) { in dmi_decode_ipmi()
[all …]
/drivers/parisc/
Ddino.c177 void __iomem *base_addr = d->hba.base_addr; in dino_cfg_read() local
180 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, in dino_cfg_read()
185 __raw_writel(v, base_addr + DINO_PCI_ADDR); in dino_cfg_read()
189 *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3)); in dino_cfg_read()
191 *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2)); in dino_cfg_read()
193 *val = readl(base_addr + DINO_CONFIG_DATA); in dino_cfg_read()
212 void __iomem *base_addr = d->hba.base_addr; in dino_cfg_write() local
215 DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where, in dino_cfg_write()
220 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); in dino_cfg_write()
221 __raw_readl(base_addr + DINO_CONFIG_DATA); in dino_cfg_write()
[all …]
Dlba_pci.c207 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
210 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
216 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
222 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
228 WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
237 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
242 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
247 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
252 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
307 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
[all …]
/drivers/net/ethernet/ti/
Dtlan.c337 outl(TLAN_HC_AD_RST, dev->base_addr + TLAN_HOST_CMD); in tlan_stop()
504 dev->base_addr = pci_io_base; in tlan_probe1()
521 dev->base_addr = ioaddr; in tlan_probe1()
579 (int)dev->base_addr, in tlan_probe1()
614 release_region(dev->base_addr, 0x10); in tlan_eisa_cleanup()
895 priv->tlan_rev = tlan_dio_read8(dev->base_addr, TLAN_DEF_REVISION); in tlan_open()
1084 outl(tail_list_phys, dev->base_addr + TLAN_CH_PARM); in tlan_start_tx()
1085 outl(TLAN_HC_GO, dev->base_addr + TLAN_HOST_CMD); in tlan_start_tx()
1138 host_int = inw(dev->base_addr + TLAN_HOST_INT); in tlan_handle_interrupt()
1144 outw(host_int, dev->base_addr + TLAN_HOST_INT); in tlan_handle_interrupt()
[all …]
Dtlan.h444 static inline u8 tlan_dio_read8(u16 base_addr, u16 internal_addr) in tlan_dio_read8() argument
446 outw(internal_addr, base_addr + TLAN_DIO_ADR); in tlan_dio_read8()
447 return inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)); in tlan_dio_read8()
454 static inline u16 tlan_dio_read16(u16 base_addr, u16 internal_addr) in tlan_dio_read16() argument
456 outw(internal_addr, base_addr + TLAN_DIO_ADR); in tlan_dio_read16()
457 return inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)); in tlan_dio_read16()
464 static inline u32 tlan_dio_read32(u16 base_addr, u16 internal_addr) in tlan_dio_read32() argument
466 outw(internal_addr, base_addr + TLAN_DIO_ADR); in tlan_dio_read32()
467 return inl(base_addr + TLAN_DIO_DATA); in tlan_dio_read32()
474 static inline void tlan_dio_write8(u16 base_addr, u16 internal_addr, u8 data) in tlan_dio_write8() argument
[all …]
/drivers/gpio/
Dgpio-zynq.c128 void __iomem *base_addr; member
236 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
239 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
244 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
247 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
252 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
292 writel_relaxed(state, gpio->base_addr + reg_offset); in zynq_gpio_set_value()
324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
[all …]
Dgpio-ts4800.c26 void __iomem *base_addr; in ts4800_gpio_probe() local
34 base_addr = devm_platform_ioremap_resource(pdev, 0); in ts4800_gpio_probe()
35 if (IS_ERR(base_addr)) in ts4800_gpio_probe()
36 return PTR_ERR(base_addr); in ts4800_gpio_probe()
48 retval = bgpio_init(chip, &pdev->dev, 2, base_addr + INPUT_REG_OFFSET, in ts4800_gpio_probe()
49 base_addr + OUTPUT_REG_OFFSET, NULL, in ts4800_gpio_probe()
50 base_addr + DIRECTION_REG_OFFSET, NULL, 0); in ts4800_gpio_probe()
/drivers/fpga/
Daltera-freeze-bridge.c33 void __iomem *base_addr; member
44 void __iomem *csr_illegal_req_addr = priv->base_addr + in altera_freeze_br_req_ack()
65 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET); in altera_freeze_br_req_ack()
69 ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET); in altera_freeze_br_req_ack()
90 void __iomem *csr_ctrl_addr = priv->base_addr + in altera_freeze_br_do_freeze()
95 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET); in altera_freeze_br_do_freeze()
125 void __iomem *csr_ctrl_addr = priv->base_addr + in altera_freeze_br_do_unfreeze()
132 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET); in altera_freeze_br_do_unfreeze()
150 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET); in altera_freeze_br_do_unfreeze()
213 void __iomem *base_addr; in altera_freeze_br_probe() local
[all …]
/drivers/net/hamradio/
Dbaycom_ser_fdx.c173 outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */ in ser12_set_divisor()
174 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
175 outb(divisor >> 8, DLM(dev->base_addr)); in ser12_set_divisor()
176 outb(0x01, LCR(dev->base_addr)); /* word length = 6 */ in ser12_set_divisor()
182 outb(0x00, THR(dev->base_addr)); in ser12_set_divisor()
258 if ((iir = inb(IIR(dev->base_addr))) & 1) in ser12_interrupt()
262 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
269 inb(LSR(dev->base_addr)); in ser12_interrupt()
273 inb(RBR(dev->base_addr)); in ser12_interrupt()
282 outb(0x00, THR(dev->base_addr)); in ser12_interrupt()
[all …]
Dbaycom_ser_hdx.c158 outb(0x81, LCR(dev->base_addr)); /* DLAB = 1 */ in ser12_set_divisor()
159 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
160 outb(0, DLM(dev->base_addr)); in ser12_set_divisor()
161 outb(0x01, LCR(dev->base_addr)); /* word length = 6 */ in ser12_set_divisor()
167 outb(0x00, THR(dev->base_addr)); in ser12_set_divisor()
193 outb(0x0e | (!!bc->modem.ser12.tx_bit), MCR(dev->base_addr)); in ser12_tx()
209 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ in ser12_rx()
339 outb(0x0d, MCR(dev->base_addr)); /* transmitter off */ in ser12_rx()
346 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); in ser12_rx()
371 if ((iir = inb(IIR(dev->base_addr))) & 1) in ser12_interrupt()
[all …]
Dyam.c465 outb(0, IER(dev->base_addr)); in yam_set_uart()
466 outb(LCR_DLAB | LCR_BIT8, LCR(dev->base_addr)); in yam_set_uart()
467 outb(divisor, DLL(dev->base_addr)); in yam_set_uart()
468 outb(0, DLM(dev->base_addr)); in yam_set_uart()
469 outb(LCR_BIT8, LCR(dev->base_addr)); in yam_set_uart()
470 outb(PTT_OFF, MCR(dev->base_addr)); in yam_set_uart()
471 outb(0x00, FCR(dev->base_addr)); in yam_set_uart()
475 inb(RBR(dev->base_addr)); in yam_set_uart()
476 inb(MSR(dev->base_addr)); in yam_set_uart()
480 outb(ENABLE_RTXINT, IER(dev->base_addr)); in yam_set_uart()
[all …]
/drivers/net/ethernet/xilinx/
Dxilinx_emaclite.c134 void __iomem *base_addr; member
164 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
166 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_enable_interrupts()
169 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_enable_interrupts()
172 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); in xemaclite_enable_interrupts()
187 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); in xemaclite_disable_interrupts()
190 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
192 drvdata->base_addr + XEL_TSR_OFFSET); in xemaclite_disable_interrupts()
195 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_disable_interrupts()
197 drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_disable_interrupts()
[all …]
/drivers/staging/axis-fifo/
Daxis-fifo.c128 void __iomem *base_addr; /* kernel space memory */ member
164 iowrite32(tmp, fifo->base_addr + addr_offset); in sysfs_write()
177 read_val = ioread32(fifo->base_addr + addr_offset); in sysfs_read()
329 iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET); in reset_ip_core()
330 iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET); in reset_ip_core()
331 iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET); in reset_ip_core()
335 fifo->base_addr + XLLF_IER_OFFSET); in reset_ip_core()
336 iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET); in reset_ip_core()
374 if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET)) { in axis_fifo_read()
385 ioread32(fifo->base_addr + XLLF_RDFO_OFFSET), in axis_fifo_read()
[all …]
/drivers/net/ethernet/8390/
Dsmc-ultra.c143 int base_addr = dev->base_addr; in do_ultra_probe() local
146 if (base_addr > 0x1ff) /* Check a single specified location. */ in do_ultra_probe()
147 return ultra_probe1(dev, base_addr); in do_ultra_probe()
148 else if (base_addr != 0) /* Don't probe at all. */ in do_ultra_probe()
278 dev->base_addr = ioaddr+ULTRA_NIC_OFFSET; in ultra_probe1()
360 dev->base_addr = pnp_port_start(idev, 0); in ultra_probe_isapnp()
365 dev->base_addr, dev->irq); in ultra_probe_isapnp()
366 if (ultra_probe1(dev, dev->base_addr) != 0) { /* Shouldn't happen. */ in ultra_probe_isapnp()
369 dev->base_addr); in ultra_probe_isapnp()
389 int ioaddr = dev->base_addr - ULTRA_NIC_OFFSET; /* ASIC addr */ in ultra_open()
[all …]
Dne.c156 #define NE_BASE (dev->base_addr)
210 unsigned long base_addr = dev->base_addr; in do_ne_probe() local
216 if (base_addr > 0x1ff) { /* Check a single specified location. */ in do_ne_probe()
217 int ret = ne_probe1(dev, base_addr); in do_ne_probe()
220 "i/o = %#lx\n", base_addr); in do_ne_probe()
223 else if (base_addr != 0) /* Don't probe at all. */ in do_ne_probe()
232 for (base_addr = 0; netcard_portlist[base_addr] != 0; base_addr++) { in do_ne_probe()
233 int ioaddr = netcard_portlist[base_addr]; in do_ne_probe()
267 dev->base_addr = pnp_port_start(idev, 0); in ne_probe_isapnp()
272 dev->base_addr, dev->irq); in ne_probe_isapnp()
[all …]
/drivers/clocksource/
Dtimer-cadence-ttc.c74 void __iomem *base_addr; member
115 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
117 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
119 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); in ttc_set_interval()
127 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
144 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); in ttc_clock_event_interrupt()
160 return (u64)readl_relaxed(timer->base_addr + in __ttc_clocksource_read()
198 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
200 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
220 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_resume()
[all …]
/drivers/clk/mediatek/
Dclk-apmixed.c22 void __iomem *base_addr; member
34 return (readl(tx->base_addr) & REF2USB_EN_MASK) == REF2USB_EN_MASK; in mtk_ref2usb_tx_is_prepared()
42 val = readl(tx->base_addr); in mtk_ref2usb_tx_prepare()
45 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
49 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
52 writel(val, tx->base_addr); in mtk_ref2usb_tx_prepare()
62 val = readl(tx->base_addr); in mtk_ref2usb_tx_unprepare()
64 writel(val, tx->base_addr); in mtk_ref2usb_tx_unprepare()
84 tx->base_addr = reg; in mtk_clk_register_ref2usb_tx()
/drivers/net/arcnet/
Dcom90io.c73 int ioaddr = dev->base_addr; in get_buffer_byte()
85 int ioaddr = dev->base_addr; in put_buffer_byte()
98 int ioaddr = dev->base_addr; in get_whole_buffer()
114 int ioaddr = dev->base_addr; in put_whole_buffer()
132 int ioaddr = dev->base_addr, status; in com90io_probe()
224 int ioaddr = dev->base_addr; in com90io_found()
234 if (!request_region(dev->base_addr, ARCNET_TOTAL_SIZE, in com90io_found()
262 release_region(dev->base_addr, ARCNET_TOTAL_SIZE); in com90io_found()
267 dev->dev_addr[0], dev->base_addr, dev->irq); in com90io_found()
282 short ioaddr = dev->base_addr; in com90io_reset()
[all …]
/drivers/net/ethernet/natsemi/
Dxtsonic.c71 (0xffff & *((volatile unsigned int *)dev->base_addr+reg))
74 *((volatile unsigned int *)dev->base_addr+reg) = val
127 unsigned int base_addr = dev->base_addr; in sonic_probe1() local
131 if (!request_mem_region(base_addr, 0x100, xtsonic_string)) in sonic_probe1()
188 release_region(dev->base_addr, SONIC_MEM_SIZE); in sonic_probe1()
219 dev->base_addr = resmem->start; in xtsonic_probe()
226 dev->base_addr, dev->dev_addr, dev->irq); in xtsonic_probe()
239 release_region(dev->base_addr, SONIC_MEM_SIZE); in xtsonic_probe()
259 release_region (dev->base_addr, SONIC_MEM_SIZE); in xtsonic_device_remove()
/drivers/gpu/drm/msm/disp/
Dmsm_disp_snapshot_util.c10 static void msm_disp_state_dump_regs(u32 **reg, u32 aligned_len, void __iomem *base_addr) in msm_disp_state_dump_regs() argument
23 addr = base_addr; in msm_disp_state_dump_regs()
24 end_addr = base_addr + aligned_len; in msm_disp_state_dump_regs()
49 static void msm_disp_state_print_regs(u32 **reg, u32 len, void __iomem *base_addr, in msm_disp_state_print_regs() argument
57 addr = base_addr; in msm_disp_state_print_regs()
65 (unsigned long)(addr - base_addr), in msm_disp_state_print_regs()
89 msm_disp_state_print_regs(&block->state, block->size, block->base_addr, p); in msm_disp_state_print()
165 void __iomem *base_addr, const char *fmt, ...) in msm_disp_snapshot_add_block() argument
185 new_blk->base_addr = base_addr; in msm_disp_snapshot_add_block()
187 msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr); in msm_disp_snapshot_add_block()
/drivers/scsi/
D3w-sas.h176 ((unsigned char __iomem *)x->base_addr + TWL_STATUS)
178 ((unsigned char __iomem *)x->base_addr + TWL_HOBQPL)
180 ((unsigned char __iomem *)x->base_addr + TWL_HOBQPH)
182 ((unsigned char __iomem *)x->base_addr + TWL_HOBDB)
184 ((unsigned char __iomem *)x->base_addr + TWL_HOBDBC)
186 ((unsigned char __iomem *)x->base_addr + TWL_HIMASK)
188 ((unsigned char __iomem *)x->base_addr + TWL_HISTAT)
190 ((unsigned char __iomem *)x->base_addr + TWL_HIBQPH)
192 ((unsigned char __iomem *)x->base_addr + TWL_HIBQPL)
194 ((unsigned char __iomem *)x->base_addr + TWL_HIBDB)
[all …]
/drivers/net/can/sja1000/
Dkvaser_pci.c141 static int number_of_sja1000_chip(void __iomem *base_addr) in number_of_sja1000_chip() argument
148 iowrite8(MOD_RM, base_addr + in number_of_sja1000_chip()
150 status = ioread8(base_addr + in number_of_sja1000_chip()
200 void __iomem *base_addr) in kvaser_pci_add_chan() argument
241 priv->reg_base = base_addr + channel * KVASER_PCI_PORT_BYTES; in kvaser_pci_add_chan()
286 void __iomem *base_addr = NULL; in kvaser_pci_init_one() local
316 base_addr = pci_iomap(pdev, 1, PCI_PORT_SIZE); in kvaser_pci_init_one()
317 if (base_addr == NULL) { in kvaser_pci_init_one()
322 no_channels = number_of_sja1000_chip(base_addr); in kvaser_pci_init_one()
331 base_addr); in kvaser_pci_init_one()
[all …]
Dems_pcmcia.c32 void __iomem *base_addr; member
89 if (readw(card->base_addr) != 0xAA55) in ems_pcmcia_interrupt()
149 writeb(EMS_CMD_UMAP, card->base_addr); in ems_pcmcia_del_card()
150 iounmap(card->base_addr); in ems_pcmcia_del_card()
175 card->base_addr = ioremap(base, EMS_PCMCIA_MEM_SIZE); in ems_pcmcia_add_card()
176 if (!card->base_addr) { in ems_pcmcia_add_card()
182 if (readw(card->base_addr) != 0xAA55) { in ems_pcmcia_add_card()
188 writeb(EMS_CMD_RESET, card->base_addr); in ems_pcmcia_add_card()
191 writeb(EMS_CMD_MAP, card->base_addr); in ems_pcmcia_add_card()
209 priv->reg_base = card->base_addr + EMS_PCMCIA_CAN_BASE_OFFSET + in ems_pcmcia_add_card()

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