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Searched refs:base_address (Results 1 – 25 of 65) sorted by relevance

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/drivers/char/xilinx_hwicap/
Dbuffer_icap.c90 return in_be32(drvdata->base_address + XHI_STATUS_REG_OFFSET); in buffer_icap_get_status()
101 static inline u32 buffer_icap_get_bram(void __iomem *base_address, in buffer_icap_get_bram() argument
104 return in_be32(base_address + (offset << 2)); in buffer_icap_get_bram()
115 static inline bool buffer_icap_busy(void __iomem *base_address) in buffer_icap_busy() argument
117 u32 status = in_be32(base_address + XHI_STATUS_REG_OFFSET); in buffer_icap_busy()
129 static inline void buffer_icap_set_size(void __iomem *base_address, in buffer_icap_set_size() argument
132 out_be32(base_address + XHI_SIZE_REG_OFFSET, data); in buffer_icap_set_size()
143 static inline void buffer_icap_set_offset(void __iomem *base_address, in buffer_icap_set_offset() argument
146 out_be32(base_address + XHI_BRAM_OFFSET_REG_OFFSET, data); in buffer_icap_set_offset()
159 static inline void buffer_icap_set_rnc(void __iomem *base_address, in buffer_icap_set_rnc() argument
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Dfifo_icap.c97 out_be32(drvdata->base_address + XHI_WF_OFFSET, data); in fifo_icap_fifo_write()
108 u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET); in fifo_icap_fifo_read()
121 out_be32(drvdata->base_address + XHI_SZ_OFFSET, data); in fifo_icap_set_read_size()
130 out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_WRITE_MASK); in fifo_icap_start_config()
140 out_be32(drvdata->base_address + XHI_CR_OFFSET, XHI_CR_READ_MASK); in fifo_icap_start_readback()
162 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_get_status()
173 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_busy()
186 return in_be32(drvdata->base_address + XHI_WFV_OFFSET); in fifo_icap_write_fifo_vacancy()
198 return in_be32(drvdata->base_address + XHI_RFO_OFFSET); in fifo_icap_read_fifo_occupancy()
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
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Dxilinx_hwicap.c664 drvdata->base_address = ioremap(drvdata->mem_start, drvdata->mem_size); in hwicap_setup()
665 if (!drvdata->base_address) { in hwicap_setup()
679 drvdata->base_address, in hwicap_setup()
694 iounmap(drvdata->base_address); in hwicap_setup()
735 iounmap(drvdata->base_address); in hwicap_remove()
/drivers/misc/ibmasm/
Dlowlevel.h41 static inline int sp_interrupt_pending(void __iomem *base_address) in sp_interrupt_pending() argument
43 return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); in sp_interrupt_pending()
46 static inline int uart_interrupt_pending(void __iomem *base_address) in uart_interrupt_pending() argument
48 return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); in uart_interrupt_pending()
51 static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask) in ibmasm_enable_interrupts() argument
53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts()
57 static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask) in ibmasm_disable_interrupts() argument
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts()
63 static inline void enable_sp_interrupts(void __iomem *base_address) in enable_sp_interrupts() argument
65 ibmasm_enable_interrupts(base_address, SP_INTR_MASK); in enable_sp_interrupts()
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Dlowlevel.c26 mfa = get_mfa_inbound(sp->base_address); in ibmasm_send_i2o_message()
33 message = get_i2o_message(sp->base_address, mfa); in ibmasm_send_i2o_message()
38 set_mfa_inbound(sp->base_address, mfa); in ibmasm_send_i2o_message()
47 void __iomem *base_address = sp->base_address; in ibmasm_interrupt_handler() local
50 if (!sp_interrupt_pending(base_address)) in ibmasm_interrupt_handler()
60 mfa = get_mfa_outbound(base_address); in ibmasm_interrupt_handler()
62 struct i2o_message *msg = get_i2o_message(base_address, mfa); in ibmasm_interrupt_handler()
67 set_mfa_outbound(base_address, mfa); in ibmasm_interrupt_handler()
Dmodule.c96 sp->base_address = pci_ioremap_bar(pdev, 0); in ibmasm_init_one()
97 if (!sp->base_address) { in ibmasm_init_one()
109 enable_sp_interrupts(sp->base_address); in ibmasm_init_one()
136 disable_sp_interrupts(sp->base_address); in ibmasm_init_one()
139 iounmap(sp->base_address); in ibmasm_init_one()
166 disable_sp_interrupts(sp->base_address); in ibmasm_remove_one()
171 iounmap(sp->base_address); in ibmasm_remove_one()
Duart.c25 iomem_base = sp->base_address + SCOUT_COM_B_BASE; in ibmasm_register_uart()
48 enable_uart_interrupts(sp->base_address); in ibmasm_register_uart()
56 disable_uart_interrupts(sp->base_address); in ibmasm_unregister_uart()
/drivers/input/serio/
Dxilinx_ps2.c68 void __iomem *base_address; /* virt. address of control registers */ member
92 sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET); in xps2_recv()
94 *byte = in_be32(drvdata->base_address + XPS2_RX_DATA_OFFSET); in xps2_recv()
112 intr_sr = in_be32(drvdata->base_address + XPS2_IPISR_OFFSET); in xps2_interrupt()
113 out_be32(drvdata->base_address + XPS2_IPISR_OFFSET, intr_sr); in xps2_interrupt()
165 sr = in_be32(drvdata->base_address + XPS2_STATUS_OFFSET); in sxps2_write()
167 out_be32(drvdata->base_address + XPS2_TX_DATA_OFFSET, c); in sxps2_write()
197 out_be32(drvdata->base_address + XPS2_GIER_OFFSET, XPS2_GIER_GIE_MASK); in sxps2_open()
198 out_be32(drvdata->base_address + XPS2_IPIER_OFFSET, XPS2_IPIXR_RX_ALL); in sxps2_open()
215 out_be32(drvdata->base_address + XPS2_GIER_OFFSET, 0x00); in sxps2_close()
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/drivers/pinctrl/bcm/
Dpinctrl-ns2-mux.c580 void __iomem *base_address; in ns2_pinmux_set() local
615 base_address = pinctrl->base0; in ns2_pinmux_set()
619 base_address = pinctrl->base1; in ns2_pinmux_set()
627 val = readl(base_address + grp->mux.offset); in ns2_pinmux_set()
630 writel(val, (base_address + grp->mux.offset)); in ns2_pinmux_set()
666 void __iomem *base_address; in ns2_pin_set_enable() local
668 base_address = pinctrl->pinconf_base; in ns2_pin_set_enable()
670 val = readl(base_address + pin_data->pin_conf.offset); in ns2_pin_set_enable()
676 writel(val, (base_address + pin_data->pin_conf.offset)); in ns2_pin_set_enable()
712 void __iomem *base_address; in ns2_pin_set_slew() local
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Dpinctrl-nsp-mux.c397 void __iomem *base_address; in nsp_pinmux_set() local
431 base_address = pinctrl->base0; in nsp_pinmux_set()
435 base_address = pinctrl->base1; in nsp_pinmux_set()
439 base_address = pinctrl->base2; in nsp_pinmux_set()
447 val = readl(base_address); in nsp_pinmux_set()
450 writel(val, base_address); in nsp_pinmux_set()
Dpinctrl-nsp-gpio.c107 void __iomem *base_address; in nsp_set_bit() local
110 base_address = chip->io_ctrl; in nsp_set_bit()
112 base_address = chip->base; in nsp_set_bit()
114 val = readl(base_address + reg); in nsp_set_bit()
120 writel(val, base_address + reg); in nsp_set_bit()
/drivers/gpu/drm/amd/display/dmub/inc/
Ddmub_cmd.h2426 void *base_address; /**< CPU base address for ring's data */ member
2436 void *base_address; /**< CPU address for the ring's data */ member
2487 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; in dmub_rb_push_front()
2515 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; in dmub_rb_out_push_front()
2542 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_front()
2582 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; in dmub_rb_peek_offset()
2603 const uint8_t *src = (const uint8_t *)(rb->base_address) + rb->rptr; in dmub_rb_out_front()
2650 const uint8_t *data = (const uint8_t *)rb->base_address + rptr; in dmub_rb_flush_pending()
2669 rb->base_address = init_params->base_address; in dmub_rb_init()
2686 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : in dmub_rb_get_return_data()
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/drivers/media/platform/imx-jpeg/
Dmxc-jpeg-hw.c12 #define print_wrapper_reg(dev, base_address, reg_offset)\ argument
13 internal_print_wrapper_reg(dev, (base_address), #reg_offset,\
15 #define internal_print_wrapper_reg(dev, base_address, reg_name, reg_offset) {\ argument
17 val = readl((base_address) + (reg_offset));\
/drivers/iio/adc/
Dad7606_par.c23 insw((unsigned long)st->base_address, buf, count); in ad7606_par16_read_block()
38 insb((unsigned long)st->base_address, buf, count * 2); in ad7606_par8_read_block()
Dad7606.h99 void __iomem *base_address; member
152 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/
Ddev.c16 phys_addr_t base_address; member
107 sf_dev->bar_base_addr = table->base_address + (sf_index * table->sf_bar_length); in mlx5_sf_dev_add()
229 table->base_address = pci_resource_start(dev->pdev, 2); in mlx5_sf_dev_table_create()
/drivers/staging/board/
Dboard.c25 static bool find_by_address(u64 base_address) in find_by_address() argument
32 if (res.start == base_address) { in find_by_address()
/drivers/staging/media/atomisp/pci/isp/kernels/ipu2_io_ls/common/
Dia_css_common_io_types.h22 unsigned int base_address; member
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_discovery.c310 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); in amdgpu_discovery_reg_base_init()
311 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); in amdgpu_discovery_reg_base_init()
319 ip->base_address; in amdgpu_discovery_reg_base_init()
/drivers/acpi/arm64/
Dgtdt.c228 !gtdt_frame->base_address || !gtdt_frame->timer_interrupt) in gtdt_parse_timer_block()
259 frame->cntbase = gtdt_frame->base_address; in gtdt_parse_timer_block()
/drivers/net/wireless/rsi/
Drsi_91x_usb.c504 u32 base_address, in rsi_usb_load_data_master_write() argument
518 status = rsi_usb_write_register_multiple(adapter, base_address, in rsi_usb_load_data_master_write()
525 base_address += block_size; in rsi_usb_load_data_master_write()
533 (adapter, base_address, in rsi_usb_load_data_master_write()
Drsi_91x_sdio.c565 u32 base_address, in rsi_sdio_load_data_master_write() argument
576 msb_address = base_address >> 16; in rsi_sdio_load_data_master_write()
594 lsb_address = (u16)base_address; in rsi_sdio_load_data_master_write()
604 base_address += block_size; in rsi_sdio_load_data_master_write()
606 if ((base_address >> 16) != msb_address) { in rsi_sdio_load_data_master_write()
625 lsb_address = (u16)base_address; in rsi_sdio_load_data_master_write()
/drivers/nfc/s3fwrn5/
Dfirmware.h59 __u32 base_address; member
/drivers/acpi/
Dviot.c164 node->mmio.base_address); in viot_get_iommu()
222 ep->address = node->mmio.base_address; in viot_parse_node()
/drivers/acpi/numa/
Dsrat.c102 (unsigned long long)p->base_address, in acpi_table_print_srat_entry()
261 start = ma->base_address; in acpi_numa_memory_affinity_init()

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