| /drivers/clk/ |
| D | clk-gate.c | 70 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
72 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
77 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
79 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
111 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
113 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
131 void __iomem *reg, u8 bit_idx, in __clk_hw_register_gate() argument
140 if (bit_idx > 15) { in __clk_hw_register_gate()
164 gate->bit_idx = bit_idx; in __clk_hw_register_gate()
186 void __iomem *reg, u8 bit_idx, in clk_register_gate() argument
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| D | clk-stm32f4.c | 49 u8 bit_idx; member
410 u8 bit_idx; member
420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
464 unsigned long flags, u8 bit_idx) in clk_register_apb_mul() argument
474 am->bit_idx = bit_idx; in clk_register_apb_mul()
539 u8 bit_idx; member
811 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
817 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
959 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, in clk_register_rgate() argument
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| D | clk-stm32h7.c | 217 void __iomem *reg, u8 bit_idx, u8 bit_rdy, in clk_register_ready_gate() argument
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate() argument
342 gate->bit_idx = bit_idx; in _get_cgate()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
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| /drivers/xen/events/ |
| D | events_2l.c | 170 int word_idx, bit_idx; in evtchn_2l_handle_events() local
180 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
181 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) in evtchn_2l_handle_events()
207 bit_idx = 0; in evtchn_2l_handle_events()
213 bit_idx = 0; /* usually scan entire word from start */ in evtchn_2l_handle_events()
228 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
235 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
241 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
244 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
247 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
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| /drivers/clk/imx/ |
| D | clk-gate2.c | 31 u8 bit_idx; member
47 reg &= ~(gate->cgr_mask << gate->bit_idx); in clk_gate2_do_shared_clks()
49 reg |= (gate->cgr_val & gate->cgr_mask) << gate->bit_idx; in clk_gate2_do_shared_clks()
89 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx, in clk_gate2_reg_is_enabled() argument
94 if (((val >> bit_idx) & cgr_mask) == cgr_val) in clk_gate2_reg_is_enabled()
108 ret = clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx, in clk_gate2_is_enabled()
138 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, in clk_hw_register_gate2() argument
153 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
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| D | clk-lpcg-scu.c | 35 u8 bit_idx; member
53 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
59 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
76 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_disable()
89 void __iomem *reg, u8 bit_idx, bool hw_gate) in __imx_clk_lpcg_scu() argument
101 clk->bit_idx = bit_idx; in __imx_clk_lpcg_scu()
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| D | clk-scu.h | 43 void __iomem *reg, u8 bit_idx, bool hw_gate);
64 void __iomem *reg, u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu_dev() argument
67 bit_idx, hw_gate); in imx_clk_lpcg_scu_dev()
72 u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu() argument
75 bit_idx, hw_gate); in imx_clk_lpcg_scu()
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| /drivers/clk/hisilicon/ |
| D | clkgate-separated.c | 27 u8 bit_idx; /* bits in enable/disable register */ member
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
58 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
72 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
86 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
104 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
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| /drivers/clk/meson/ |
| D | axg.c | 338 .bit_idx = 27,
365 .bit_idx = 28,
403 .bit_idx = 29,
429 .bit_idx = 30,
457 .bit_idx = 31,
523 .bit_idx = 14,
574 .bit_idx = 14,
630 .bit_idx = 14,
681 .bit_idx = 0,
831 .bit_idx = 4,
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| D | meson8b.c | 278 .bit_idx = 27,
306 .bit_idx = 28,
334 .bit_idx = 29,
362 .bit_idx = 30,
390 .bit_idx = 31,
455 .bit_idx = 14,
500 .bit_idx = 14,
545 .bit_idx = 14,
602 .bit_idx = 7,
784 .bit_idx = 8,
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| D | gxbb.c | 572 .bit_idx = 27,
599 .bit_idx = 28,
637 .bit_idx = 29,
663 .bit_idx = 30,
689 .bit_idx = 31,
776 .bit_idx = 14,
828 .bit_idx = 14,
871 .bit_idx = 14,
933 .bit_idx = 7,
984 .bit_idx = 8,
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| D | g12a-aoclk.c | 48 .bit_idx = (_bit), \
80 .bit_idx = 14,
107 .bit_idx = 31,
180 .bit_idx = 30,
198 .bit_idx = 31,
271 .bit_idx = 30,
359 .bit_idx = 8,
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| D | g12a.c | 220 .bit_idx = 24,
237 .bit_idx = 24,
293 .bit_idx = 24,
330 .bit_idx = 20,
1134 .bit_idx = 1,
1153 .bit_idx = 1,
1213 .bit_idx = 1,
1247 .bit_idx = 17,
1281 .bit_idx = 18,
1325 .bit_idx = 23,
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| D | axg-aoclk.c | 39 .bit_idx = (_bit), \
63 .bit_idx = 14,
78 .bit_idx = 31,
161 .bit_idx = 30,
249 .bit_idx = 8,
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| D | clk-regmap.c | 18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
40 val ^= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
42 val &= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
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| D | gxbb-aoclk.c | 28 .bit_idx = (_bit), \
51 .bit_idx = 6,
66 .bit_idx = 31,
145 .bit_idx = 30,
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| D | clk-regmap.h | 46 u8 bit_idx; member
121 .bit_idx = (_bit), \
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| /drivers/clk/actions/ |
| D | owl-gate.c | 27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
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| D | owl-gate.h | 18 u8 bit_idx; member
30 .bit_idx = _bit_idx, \
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| D | owl-pll.c | 119 return !!(reg & BIT(pll_hw->bit_idx)); in owl_pll_is_enabled()
130 reg |= BIT(pll_hw->bit_idx); in owl_pll_set()
132 reg &= ~BIT(pll_hw->bit_idx); in owl_pll_set()
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| D | owl-pll.h | 27 u8 bit_idx; member
46 .bit_idx = _bit_idx, \
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| /drivers/clk/mvebu/ |
| D | cp110-system-controller.c | 116 u8 bit_idx; member
126 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
136 BIT(gate->bit_idx), 0); in cp110_gate_disable()
146 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
157 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
176 gate->bit_idx = bit_idx; in cp110_register_gate()
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| /drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 117 clkc_data->mod_clk_en.bit_idx = 15; in meson_mx_sdhc_register_clkc()
125 clkc_data->tx_clk_en.bit_idx = 14; in meson_mx_sdhc_register_clkc()
133 clkc_data->rx_clk_en.bit_idx = 13; in meson_mx_sdhc_register_clkc()
141 clkc_data->sd_clk_en.bit_idx = 12; in meson_mx_sdhc_register_clkc()
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| /drivers/clk/ralink/ |
| D | clk-mt7621.c | 55 u32 bit_idx; member
64 .bit_idx = _shift \
101 clk_gate->bit_idx, clk_gate->bit_idx); in mt7621_gate_enable()
109 regmap_update_bits(sysc, SYSC_REG_CLKCFG1, clk_gate->bit_idx, 0); in mt7621_gate_disable()
121 return val & BIT(clk_gate->bit_idx); in mt7621_gate_is_enabled()
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| /drivers/clk/keystone/ |
| D | syscon-clk.c | 22 u32 bit_idx; member
82 priv->idx = BIT(data->bit_idx); in ti_syscon_gate_clk_register()
139 .bit_idx = (_bit_idx), \
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