| /drivers/pinctrl/ |
| D | pinctrl-bm1880.c | 1015 u32 *regval, u32 bit_offset) in bm1880_pinconf_drv_set() argument
1028 _regval &= ~(width << bit_offset); in bm1880_pinconf_drv_set()
1029 _regval |= (0 << bit_offset); in bm1880_pinconf_drv_set()
1032 _regval &= ~(width << bit_offset); in bm1880_pinconf_drv_set()
1033 _regval |= (1 << bit_offset); in bm1880_pinconf_drv_set()
1036 _regval &= ~(width << bit_offset); in bm1880_pinconf_drv_set()
1037 _regval |= (2 << bit_offset); in bm1880_pinconf_drv_set()
1040 _regval &= ~(width << bit_offset); in bm1880_pinconf_drv_set()
1041 _regval |= (3 << bit_offset); in bm1880_pinconf_drv_set()
1044 _regval &= ~(width << bit_offset); in bm1880_pinconf_drv_set()
[all …]
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| /drivers/gpio/ |
| D | gpio-xgene.c | 41 u32 bit_offset; in xgene_gpio_get() local
44 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get()
45 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); in xgene_gpio_get()
52 u32 setval, bit_offset; in __xgene_gpio_set() local
55 bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK; in __xgene_gpio_set()
59 setval |= BIT(bit_offset); in __xgene_gpio_set()
61 setval &= ~BIT(bit_offset); in __xgene_gpio_set()
78 unsigned long bank_offset, bit_offset; in xgene_gpio_get_direction() local
81 bit_offset = GPIO_BIT_OFFSET(offset); in xgene_gpio_get_direction()
83 if (ioread32(chip->base + bank_offset) & BIT(bit_offset)) in xgene_gpio_get_direction()
[all …]
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| D | gpio-pcie-idio-24.c | 377 const unsigned long bit_offset = irqd_to_hwirq(data) - 24; in idio_24_irq_mask() local
379 const unsigned long bank_offset = bit_offset / 8; in idio_24_irq_mask()
384 idio24gpio->irq_mask &= ~BIT(bit_offset); in idio_24_irq_mask()
407 const unsigned long bit_offset = irqd_to_hwirq(data) - 24; in idio_24_irq_unmask() local
408 const unsigned long bank_offset = bit_offset / 8; in idio_24_irq_unmask()
414 idio24gpio->irq_mask |= BIT(bit_offset); in idio_24_irq_unmask()
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| /drivers/acpi/acpica/ |
| D | hwregs.c | 69 if (!reg->bit_offset && reg->bit_width && in acpi_hw_get_access_bit_width()
77 ACPI_ROUND_UP_POWER_OF_TWO_8(reg->bit_offset + in acpi_hw_get_access_bit_width()
167 ACPI_ROUND_UP(reg->bit_offset + reg->bit_width, access_width); in acpi_hw_validate_register()
200 u8 bit_offset; in acpi_hw_read() local
221 bit_width = reg->bit_offset + reg->bit_width; in acpi_hw_read()
222 bit_offset = reg->bit_offset; in acpi_hw_read()
230 if (bit_offset >= access_width) { in acpi_hw_read()
232 bit_offset -= access_width; in acpi_hw_read()
295 u8 bit_offset; in acpi_hw_write() local
312 bit_width = reg->bit_offset + reg->bit_width; in acpi_hw_write()
[all …]
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| D | dsopcode.c | 83 u32 bit_offset; in acpi_ds_init_buffer_field() local
127 bit_offset = offset; in acpi_ds_init_buffer_field()
144 bit_offset = offset; in acpi_ds_init_buffer_field()
153 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
162 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
171 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
180 bit_offset = 8 * offset; in acpi_ds_init_buffer_field()
196 if ((bit_offset + bit_count) > (8 * (u32)buffer_desc->buffer.length)) { in acpi_ds_init_buffer_field()
202 bit_offset, bit_count, in acpi_ds_init_buffer_field()
214 bit_offset, bit_count); in acpi_ds_init_buffer_field()
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| /drivers/soc/tegra/fuse/ |
| D | fuse-tegra.c | 101 .bit_offset = 0,
107 .bit_offset = 0,
113 .bit_offset = 0,
119 .bit_offset = 0,
125 .bit_offset = 0,
131 .bit_offset = 0,
137 .bit_offset = 0,
143 .bit_offset = 0,
149 .bit_offset = 0,
155 .bit_offset = 0,
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | bit.c | 30 if (likely(bios->bit_offset)) { in bit_entry()
31 u8 entries = nvbios_rd08(bios, bios->bit_offset + 10); in bit_entry()
32 u32 entry = bios->bit_offset + 12; in bit_entry()
42 entry += nvbios_rd08(bios, bios->bit_offset + 9); in bit_entry()
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| D | base.c | 181 bios->bit_offset = nvbios_findstr(bios->data, bios->size, in nvkm_bios_new()
183 if (bios->bit_offset) in nvkm_bios_new()
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| /drivers/gpu/drm/omapdrm/ |
| D | tcm-sita.c | 95 unsigned long bit_offset = (offset > 0) ? offset / slot_bytes : 0; in l2r_t2b() local
96 unsigned long curr_bit = bit_offset; in l2r_t2b()
109 if (bit_offset > 0 && (*pos % slots_per_band != bit_offset)) { in l2r_t2b()
110 curr_bit = ALIGN(*pos, slots_per_band) + bit_offset; in l2r_t2b()
116 curr_bit = ALIGN(*pos, slot_stride) + bit_offset; in l2r_t2b()
147 if (bit_offset > 0) in l2r_t2b()
148 curr_bit = ALIGN(*pos, slots_per_band) + bit_offset; in l2r_t2b()
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| /drivers/nvmem/ |
| D | core.c | 53 int bit_offset; member
463 cell->bit_offset = info->bit_offset; in nvmem_cell_info_to_nvmem_cell_nodup()
467 cell->bytes = DIV_ROUND_UP(cell->nbits + cell->bit_offset, in nvmem_cell_info_to_nvmem_cell_nodup()
712 cell->bit_offset = be32_to_cpup(addr++); in nvmem_add_cells_from_of()
718 cell->nbits + cell->bit_offset, in nvmem_add_cells_from_of()
1360 int i, extra, bit_offset = cell->bit_offset; in nvmem_shift_read_buffer_in_place() local
1363 if (bit_offset) { in nvmem_shift_read_buffer_in_place()
1365 *b++ >>= bit_offset; in nvmem_shift_read_buffer_in_place()
1370 *p |= *b << (BITS_PER_BYTE - bit_offset); in nvmem_shift_read_buffer_in_place()
1373 *b++ >>= bit_offset; in nvmem_shift_read_buffer_in_place()
[all …]
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| /drivers/net/wireless/ralink/rt2x00/ |
| D | rt2x00reg.h | 148 u8 bit_offset; member
153 u16 bit_offset; member
158 u32 bit_offset; member
240 ((__field).bit_offset)) & \
248 ((__field).bit_offset); \
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| D | rt73usb.c | 308 field.bit_offset = (3 * key->hw_key_idx); in rt73usb_config_shared_key()
309 field.bit_mask = 0x7 << field.bit_offset; in rt73usb_config_shared_key()
315 field.bit_offset = (3 * (key->hw_key_idx - 8)); in rt73usb_config_shared_key()
316 field.bit_mask = 0x7 << field.bit_offset; in rt73usb_config_shared_key()
2252 field.bit_offset = (queue_idx & 1) * 16; in rt73usb_conf_tx()
2253 field.bit_mask = 0xffff << field.bit_offset; in rt73usb_conf_tx()
2260 field.bit_offset = queue_idx * 4; in rt73usb_conf_tx()
2261 field.bit_mask = 0xf << field.bit_offset; in rt73usb_conf_tx()
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| /drivers/acpi/apei/ |
| D | apei-base.c | 64 *val >>= entry->register_region.bit_offset; in __apei_exec_read_register()
104 val <<= entry->register_region.bit_offset; in __apei_exec_write_register()
110 valr &= ~(entry->mask << entry->register_region.bit_offset); in __apei_exec_write_register()
574 u32 bit_width, bit_offset, access_size_code, space_id; in apei_check_gar() local
577 bit_offset = reg->bit_offset; in apei_check_gar()
584 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
592 *paddr, bit_width, bit_offset, access_size_code, in apei_check_gar()
599 if (bit_width == 32 && bit_offset == 0 && (*paddr & 0x03) == 0 && in apei_check_gar()
602 else if (bit_width == 64 && bit_offset == 0 && (*paddr & 0x07) == 0 && in apei_check_gar()
606 if ((bit_width + bit_offset) > *access_bit_width) { in apei_check_gar()
[all …]
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| /drivers/irqchip/ |
| D | irq-meson-gpio.c | 170 unsigned int bit_offset; in meson8_gpio_irq_sel_pin() local
173 bit_offset = REG_PIN_SEL_SHIFT(channel); in meson8_gpio_irq_sel_pin()
176 ctl->params->pin_sel_mask << bit_offset, in meson8_gpio_irq_sel_pin()
177 hwirq << bit_offset); in meson8_gpio_irq_sel_pin()
185 unsigned int bit_offset; in meson_a1_gpio_irq_sel_pin() local
187 bit_offset = ((channel % 2) == 0) ? 0 : 16; in meson_a1_gpio_irq_sel_pin()
191 ctl->params->pin_sel_mask << bit_offset, in meson_a1_gpio_irq_sel_pin()
192 hwirq << bit_offset); in meson_a1_gpio_irq_sel_pin()
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| /drivers/acpi/ |
| D | processor_throttling.c | 462 throttling->control_register.bit_offset) > 32) { in acpi_processor_get_throttling_control()
469 throttling->status_register.bit_offset) > 32) { in acpi_processor_get_throttling_control()
754 u32 bit_width, bit_offset; in acpi_read_throttling_status() local
764 bit_offset = throttling->status_register.bit_offset; in acpi_read_throttling_status()
768 (u32) (bit_width + bit_offset)); in acpi_read_throttling_status()
770 *value = (u64) ((ptc_value >> bit_offset) & ptc_mask); in acpi_read_throttling_status()
786 u32 bit_width, bit_offset; in acpi_write_throttling_state() local
796 bit_offset = throttling->control_register.bit_offset; in acpi_write_throttling_state()
802 (u32) (ptc_value << bit_offset), in acpi_write_throttling_state()
803 (u32) (bit_width + bit_offset)); in acpi_write_throttling_state()
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| D | acpi_lpit.c | 43 u64 mask = GENMASK_ULL(residency_info_ffh.gaddr.bit_offset + in lpit_read_residency_counter_us()
45 residency_info_ffh.gaddr.bit_offset); in lpit_read_residency_counter_us()
48 *counter >>= residency_info_ffh.gaddr.bit_offset; in lpit_read_residency_counter_us()
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| /drivers/clk/imx/ |
| D | clk-imx8qxp-lpcg.c | 183 unsigned int bit_offset[IMX_LPCG_MAX_CLKS]; in imx_lpcg_parse_clks_from_dt() local
223 ret = of_property_read_u32_array(np, "clock-indices", bit_offset, in imx_lpcg_parse_clks_from_dt()
250 idx = bit_offset[i] / 4; in imx_lpcg_parse_clks_from_dt()
260 bit_offset[i], false); in imx_lpcg_parse_clks_from_dt()
281 idx = bit_offset[i] / 4; in imx_lpcg_parse_clks_from_dt()
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| /drivers/watchdog/ |
| D | wdat_wdt.c | 147 x >>= gas->bit_offset; in wdat_wdt_run_action()
157 x >>= gas->bit_offset; in wdat_wdt_run_action()
165 x <<= gas->bit_offset; in wdat_wdt_run_action()
170 y = y & ~(mask << gas->bit_offset); in wdat_wdt_run_action()
181 x <<= gas->bit_offset; in wdat_wdt_run_action()
186 y = y & ~(mask << gas->bit_offset); in wdat_wdt_run_action()
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| /drivers/pinctrl/sprd/ |
| D | pinctrl-sprd.h | 31 .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
48 unsigned long bit_offset; member
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| D | pinctrl-sprd.c | 110 unsigned long bit_offset; member
451 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); in sprd_pinconf_get()
726 << pin->bit_offset); in sprd_pinconf_set()
728 << pin->bit_offset; in sprd_pinconf_set()
796 pin->bit_offset) & PINCTRL_BIT_MASK(pin->bit_width); in sprd_pinconf_get_config()
1018 pin->bit_offset = sprd_soc_pin_info[i].bit_offset; in sprd_pinctrl_add_pins()
1037 pin->bit_offset, pin->bit_width, pin->reg); in sprd_pinctrl_add_pins()
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| /drivers/cpufreq/ |
| D | pcc-cpufreq.c | 56 u8 bit_offset; member
489 doorbell.bit_offset = reg_resource->bit_offset; in pcc_cpufreq_probe()
495 doorbell.space_id, doorbell.bit_width, doorbell.bit_offset, in pcc_cpufreq_probe()
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| /drivers/xen/ |
| D | xen-acpi-processor.c | 79 dst_cx->reg.bit_offset = 0; in push_cxx_to_hypervisor()
85 dst_cx->reg.bit_offset = 2; in push_cxx_to_hypervisor()
199 dst_pct->bit_offset = pct->bit_offset; in xen_copy_pct_data()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | bios.h | 15 u32 bit_offset; member
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| /drivers/clk/ti/ |
| D | clkctrl.c | 59 int bit_offset; member
246 entry->bit_offset == clkspec->args[1]) { in _ti_omap4_clkctrl_xlate()
327 clkctrl_clk->bit_offset = bit; in _ti_clkctrl_clk_register()
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| /drivers/block/drbd/ |
| D | drbd_main.c | 1121 if (c->bit_offset >= c->bm_bits) in fill_bitmap_rle_bits()
1138 tmp = (toggle == 0) ? _drbd_bm_find_next_zero(device, c->bit_offset) in fill_bitmap_rle_bits()
1139 : _drbd_bm_find_next(device, c->bit_offset); in fill_bitmap_rle_bits()
1142 rl = tmp - c->bit_offset; in fill_bitmap_rle_bits()
1160 "t:%u bo:%lu\n", toggle, c->bit_offset); in fill_bitmap_rle_bits()
1174 c->bit_offset = tmp; in fill_bitmap_rle_bits()
1175 } while (c->bit_offset < c->bm_bits); in fill_bitmap_rle_bits()
1182 c->bit_offset -= plain_bits; in fill_bitmap_rle_bits()
1184 c->bit_offset = c->word_offset * BITS_PER_LONG; in fill_bitmap_rle_bits()
1225 if (c->bit_offset >= c->bm_bits) in send_bitmap_rle_or_plain()
[all …]
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