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Searched refs:block_offset (Results 1 – 18 of 18) sorted by relevance

/drivers/soundwire/
Dgeneric_bandwidth_allocation.c34 int block_offset; member
48 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
84 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
134 t_data.block_offset = port_bo; in sdw_compute_master_ports()
147 int block_offset, port_bo, i; in _sdw_compute_port_params() local
152 block_offset = 1; in _sdw_compute_port_params()
158 block_offset += m_rt->ch_count * in _sdw_compute_port_params()
160 port_bo = block_offset; in _sdw_compute_port_params()
/drivers/gpu/drm/radeon/
Ddce6_afmt.c34 u32 block_offset, u32 reg) in dce6_endpoint_rreg() argument
40 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce6_endpoint_rreg()
41 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); in dce6_endpoint_rreg()
48 u32 block_offset, u32 reg, u32 v) in dce6_endpoint_wreg() argument
54 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce6_endpoint_wreg()
56 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, in dce6_endpoint_wreg()
58 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce6_endpoint_wreg()
/drivers/phy/cadence/
Dphy-cadence-sierra.c41 #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ argument
42 ((0x4000 << (block_offset)) + \
145 #define SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset) \ argument
146 (0xc000 << (block_offset))
622 u32 block_offset, u8 reg_offset_shift, in cdns_regmap_init() argument
632 ctx->base = base + block_offset; in cdns_regmap_init()
707 u32 block_offset; in cdns_regmap_init_blocks() local
711 block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift, in cdns_regmap_init_blocks()
713 regmap = cdns_regmap_init(dev, base, block_offset, in cdns_regmap_init_blocks()
732 block_offset = SIERRA_PHY_CONFIG_CTRL_OFFSET(block_offset_shift); in cdns_regmap_init_blocks()
[all …]
Dphy-cadence-torrent.c43 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ argument
44 ((0x4000 << (block_offset)) + \
47 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ argument
48 ((0x8000 << (block_offset)) + \
51 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ argument
52 (0xC000 << (block_offset))
54 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ argument
55 ((0xD000 << (block_offset)) + \
58 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ argument
59 (0xE000 << (block_offset))
[all …]
/drivers/md/
Ddm-verity-fec.c125 u64 rsb, int byte_index, unsigned block_offset, in fec_decode_bufs() argument
133 par = fec_read_parity(v, rsb, block_offset, &offset, &buf); in fec_decode_bufs()
150 fio->output[block_offset] = block[byte_index]; in fec_decode_bufs()
152 block_offset++; in fec_decode_bufs()
153 if (block_offset >= 1 << v->data_dev_block_bits) in fec_decode_bufs()
161 par = fec_read_parity(v, rsb, block_offset, &offset, &buf); in fec_decode_bufs()
201 u64 rsb, u64 target, unsigned block_offset, in fec_read_bufs() argument
287 k = fec_buffer_rs_index(n, j) + block_offset; in fec_read_bufs()
/drivers/net/wireless/intersil/orinoco/
Dfw.c48 __le32 block_offset; /* Offset of block data from eof header */ member
69 if ((hdrsize + le32_to_cpu(hdr->block_offset)) > len) in validate_fw()
161 le32_to_cpu(hdr->block_offset)); in orinoco_dl_firmware()
/drivers/cxl/core/
Dregs.c192 phys_addr += map->block_offset; in cxl_map_component_regs()
212 phys_addr += map->block_offset; in cxl_map_device_regs()
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dhv_vhca.c340 int block_offset = 0; in mlx5_hv_vhca_agent_write() local
350 len, &block_offset); in mlx5_hv_vhca_agent_write()
/drivers/cxl/
Dcxl.h143 u64 block_offset; member
Dpci.c1148 map->block_offset = offset; in cxl_mem_setup_regs()
/drivers/input/rmi4/
Drmi_f34.h134 __le16 block_offset; member
/drivers/dma/
Dfsl-qdma.c137 (((fsl_qdma_engine)->block_offset) * (x))
224 int block_offset; member
1179 fsl_qdma->block_offset = blk_off; in fsl_qdma_probe()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c123 u32 block_offset, u32 reg) in dce_v8_0_audio_endpt_rreg() argument
129 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v8_0_audio_endpt_rreg()
130 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v8_0_audio_endpt_rreg()
137 u32 block_offset, u32 reg, u32 v) in dce_v8_0_audio_endpt_wreg() argument
142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v8_0_audio_endpt_wreg()
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce_v8_0_audio_endpt_wreg()
Ddce_v6_0.c126 u32 block_offset, u32 reg) in dce_v6_0_audio_endpt_rreg() argument
132 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v6_0_audio_endpt_rreg()
133 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v6_0_audio_endpt_rreg()
140 u32 block_offset, u32 reg, u32 v) in dce_v6_0_audio_endpt_wreg() argument
145 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, in dce_v6_0_audio_endpt_wreg()
147 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce_v6_0_audio_endpt_wreg()
Ddce_v10_0.c175 u32 block_offset, u32 reg) in dce_v10_0_audio_endpt_rreg() argument
181 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v10_0_audio_endpt_rreg()
182 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v10_0_audio_endpt_rreg()
189 u32 block_offset, u32 reg, u32 v) in dce_v10_0_audio_endpt_wreg() argument
194 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v10_0_audio_endpt_wreg()
195 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce_v10_0_audio_endpt_wreg()
Ddce_v11_0.c193 u32 block_offset, u32 reg) in dce_v11_0_audio_endpt_rreg() argument
199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v11_0_audio_endpt_rreg()
200 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); in dce_v11_0_audio_endpt_rreg()
207 u32 block_offset, u32 reg, u32 v) in dce_v11_0_audio_endpt_wreg() argument
212 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); in dce_v11_0_audio_endpt_wreg()
213 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); in dce_v11_0_audio_endpt_wreg()
/drivers/infiniband/core/
Dverbs.c2969 unsigned int block_offset; in __rdma_block_iter_next() local
2976 block_offset = biter->__dma_addr & (BIT_ULL(biter->__pg_bit) - 1); in __rdma_block_iter_next()
2977 sg_delta = BIT_ULL(biter->__pg_bit) - block_offset; in __rdma_block_iter_next()
/drivers/net/ethernet/intel/i40e/
Di40e_main.c10748 u16 block_offset = 0xffff; in i40e_get_oem_version() local
10763 i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset); in i40e_get_oem_version()
10764 if (block_offset == 0xffff) in i40e_get_oem_version()
10768 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET, in i40e_get_oem_version()
10774 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET, in i40e_get_oem_version()
10779 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET, in i40e_get_oem_version()
10781 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET, in i40e_get_oem_version()