| /drivers/pwm/ |
| D | pwm-berlin.c | 59 static inline u32 berlin_pwm_readl(struct berlin_pwm_chip *bpc, in berlin_pwm_readl() argument
62 return readl_relaxed(bpc->base + channel * 0x10 + offset); in berlin_pwm_readl()
65 static inline void berlin_pwm_writel(struct berlin_pwm_chip *bpc, in berlin_pwm_writel() argument
69 writel_relaxed(value, bpc->base + channel * 0x10 + offset); in berlin_pwm_writel()
93 struct berlin_pwm_chip *bpc = to_berlin_pwm_chip(chip); in berlin_pwm_config() local
98 cycles = clk_get_rate(bpc->clk); in berlin_pwm_config()
115 value = berlin_pwm_readl(bpc, pwm->hwpwm, BERLIN_PWM_CONTROL); in berlin_pwm_config()
120 berlin_pwm_writel(bpc, pwm->hwpwm, value, BERLIN_PWM_CONTROL); in berlin_pwm_config()
122 berlin_pwm_writel(bpc, pwm->hwpwm, duty, BERLIN_PWM_DUTY); in berlin_pwm_config()
123 berlin_pwm_writel(bpc, pwm->hwpwm, period, BERLIN_PWM_TCNT); in berlin_pwm_config()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dsc/ |
| D | rc_calc_fpu.c | 31 #define table_hash(mode, bpc, max_min) ((mode << 16) | (bpc << 8) | max_min) argument
37 #define TABLE_CASE(mode, bpc, max) case (table_hash(mode, BPC_##bpc, max)): \ argument
38 table = qp_table_##mode##_##bpc##bpc_##max; \
39 …table_size = sizeof(qp_table_##mode##_##bpc##bpc_##max)/sizeof(*qp_table_##mode##_##bpc##bpc_##max…
74 static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, in get_qp_set() argument
78 int sel = table_hash(mode, bpc, max_min); in get_qp_set()
177 enum bits_per_comp bpc, in _do_calc_rc_params() argument
199 …rc->rc_quant_incr_limit0 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == … in _do_calc_rc_params()
200 …rc->rc_quant_incr_limit1 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == … in _do_calc_rc_params()
207 … = median3(0, (12 + (int) (0.09 * min(34, slice_height - 8))), (int)((3 * bpc * 3) - (3 * bpp_gro… in _do_calc_rc_params()
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| /drivers/gpu/drm/panel/ |
| D | panel-simple.c | 72 unsigned int bpc; member
305 connector->display_info.bpc = panel->desc->bpc; in panel_simple_get_non_edid_modes()
747 desc->bpc != 6); in panel_simple_probe()
750 desc->bpc != 8); in panel_simple_probe()
753 if (desc->bpc != 6 && desc->bpc != 8 && desc->bpc != 10) in panel_simple_probe()
754 dev_warn(dev, "Expected bpc in {6,8,10} but got: %u\n", desc->bpc); in panel_simple_probe()
757 if (desc->bpc != 6 && desc->bpc != 8) in panel_simple_probe()
758 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); in panel_simple_probe()
775 if (desc->bpc != 6 && desc->bpc != 8) in panel_simple_probe()
776 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); in panel_simple_probe()
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| D | panel-boe-himax8279d.c | 32 unsigned int bpc; member
234 connector->display_info.bpc = pinfo->desc->bpc; in boe_panel_get_modes()
525 .bpc = 8,
825 .bpc = 8,
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| D | panel-boe-tv101wum-nl6.c | 23 unsigned int bpc; member
608 .bpc = 8,
635 .bpc = 8,
663 .bpc = 8,
690 .bpc = 8,
718 .bpc = 8,
751 connector->display_info.bpc = boe->desc->bpc; in boe_panel_get_modes()
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| D | panel-seiko-43wvf1g.c | 28 unsigned int bpc; member
111 connector->display_info.bpc = panel->desc->bpc; in seiko_panel_get_fixed_modes()
301 .bpc = 8,
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| D | panel-innolux-p079zca.c | 32 unsigned int bpc; member
223 .bpc = 8,
370 .bpc = 8,
405 connector->display_info.bpc = innolux->desc->bpc; in innolux_panel_get_modes()
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| D | panel-olimex-lcd-olinuxino.c | 45 u32 bpc; member
187 connector->display_info.bpc = lcd_info->bpc; in lcd_olinuxino_get_modes()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_qp_tables.c | 287 if (bpc == (_bpc)) \
288 return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
291 u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i) in intel_lookup_range_min_qp() argument
297 MISSING_CASE(bpc); in intel_lookup_range_min_qp()
301 u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i) in intel_lookup_range_max_qp() argument
307 MISSING_CASE(bpc); in intel_lookup_range_max_qp()
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| D | intel_qp_tables.h | 11 u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
12 u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
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| D | intel_hdmi.c | 1876 static int intel_hdmi_port_clock(int clock, int bpc) in intel_hdmi_port_clock() argument
1883 return clock * bpc / 8; in intel_hdmi_port_clock()
1887 int bpc, bool has_hdmi_sink, bool ycbcr420_output) in intel_hdmi_bpc_possible() argument
1893 switch (bpc) { in intel_hdmi_bpc_possible()
1919 MISSING_CASE(bpc); in intel_hdmi_bpc_possible()
1998 int bpc, bool has_hdmi_sink, bool ycbcr420_output) in intel_hdmi_deep_color_possible() argument
2005 if (crtc_state->pipe_bpp < bpc * 3) in intel_hdmi_deep_color_possible()
2012 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) in intel_hdmi_deep_color_possible()
2020 int bpc) in hdmi_deep_color_possible() argument
2036 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && in hdmi_deep_color_possible()
[all …]
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| D | intel_dp.c | 954 const struct intel_crtc_state *crtc_state, int bpc) in intel_dp_hdmi_tmds_clock() argument
956 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; in intel_dp_hdmi_tmds_clock()
965 const struct intel_crtc_state *crtc_state, int bpc) in intel_dp_hdmi_tmds_clock_valid() argument
967 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); in intel_dp_hdmi_tmds_clock_valid()
982 int bpc) in intel_dp_hdmi_deep_color_possible() argument
985 return intel_hdmi_deep_color_possible(crtc_state, bpc, in intel_dp_hdmi_deep_color_possible()
988 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); in intel_dp_hdmi_deep_color_possible()
996 int bpp, bpc; in intel_dp_max_bpp() local
998 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1001 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); in intel_dp_max_bpp()
[all …]
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_drm_ddp_comp.c | 129 unsigned int bpc, unsigned int cfg, in mtk_dither_set_common() argument
133 if (bpc == 0) in mtk_dither_set_common()
136 if (bpc >= MTK_MIN_BPC) { in mtk_dither_set_common()
140 DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | in mtk_dither_set_common()
141 DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | in mtk_dither_set_common()
145 DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | in mtk_dither_set_common()
146 DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | in mtk_dither_set_common()
147 DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | in mtk_dither_set_common()
148 DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), in mtk_dither_set_common()
154 static void mtk_dither_set(struct device *dev, unsigned int bpc, in mtk_dither_set() argument
[all …]
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| D | mtk_disp_drv.h | 16 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
26 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
35 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
39 unsigned int bpc, unsigned int cfg,
52 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
65 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
91 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
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| D | mtk_drm_ddp_comp.h | 47 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
96 unsigned int vrefresh, unsigned int bpc, in mtk_ddp_comp_config() argument
100 comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt); in mtk_ddp_comp_config()
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| D | mtk_drm_crtc.c | 293 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; in mtk_crtc_ddp_hw_init() local
312 if (connector->display_info.bpc != 0 && in mtk_crtc_ddp_hw_init()
313 bpc > connector->display_info.bpc) in mtk_crtc_ddp_hw_init()
314 bpc = connector->display_info.bpc; in mtk_crtc_ddp_hw_init()
353 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); in mtk_crtc_ddp_hw_init()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_connectors.c | 104 int bpc = 8; in amdgpu_connector_get_monitor_bpc() local
112 if (connector->display_info.bpc) in amdgpu_connector_get_monitor_bpc()
113 bpc = connector->display_info.bpc; in amdgpu_connector_get_monitor_bpc()
120 if (connector->display_info.bpc) in amdgpu_connector_get_monitor_bpc()
121 bpc = connector->display_info.bpc; in amdgpu_connector_get_monitor_bpc()
129 if (connector->display_info.bpc) in amdgpu_connector_get_monitor_bpc()
130 bpc = connector->display_info.bpc; in amdgpu_connector_get_monitor_bpc()
135 if (connector->display_info.bpc) in amdgpu_connector_get_monitor_bpc()
136 bpc = connector->display_info.bpc; in amdgpu_connector_get_monitor_bpc()
145 bpc = 6; in amdgpu_connector_get_monitor_bpc()
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| D | atombios_crtc.c | 318 int bpc = amdgpu_crtc->bpc; in amdgpu_atombios_crtc_adjust_pll() local
359 switch (bpc) { in amdgpu_atombios_crtc_adjust_pll()
586 int bpc, in amdgpu_atombios_crtc_program_pll() argument
655 switch (bpc) { in amdgpu_atombios_crtc_program_pll()
686 switch (bpc) { in amdgpu_atombios_crtc_program_pll()
714 switch (bpc) { in amdgpu_atombios_crtc_program_pll()
757 amdgpu_crtc->bpc = 8; in amdgpu_atombios_crtc_prepare_pll()
773 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector); in amdgpu_atombios_crtc_prepare_pll()
832 (amdgpu_crtc->bpc > 8)) in amdgpu_atombios_crtc_set_pll()
863 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in amdgpu_atombios_crtc_set_pll()
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| /drivers/gpu/drm/radeon/ |
| D | radeon_connectors.c | 126 int bpc = 8; in radeon_get_monitor_bpc() local
134 if (connector->display_info.bpc) in radeon_get_monitor_bpc()
135 bpc = connector->display_info.bpc; in radeon_get_monitor_bpc()
142 if (connector->display_info.bpc) in radeon_get_monitor_bpc()
143 bpc = connector->display_info.bpc; in radeon_get_monitor_bpc()
151 if (connector->display_info.bpc) in radeon_get_monitor_bpc()
152 bpc = connector->display_info.bpc; in radeon_get_monitor_bpc()
157 if (connector->display_info.bpc) in radeon_get_monitor_bpc()
158 bpc = connector->display_info.bpc; in radeon_get_monitor_bpc()
167 bpc = 6; in radeon_get_monitor_bpc()
[all …]
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| D | evergreen_hdmi.c | 73 int bpc = 8; in evergreen_hdmi_update_acr() local
77 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr()
80 if (bpc > 8) in evergreen_hdmi_update_acr()
318 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) in dce4_hdmi_set_color_depth() argument
329 switch (bpc) { in dce4_hdmi_set_color_depth()
336 connector->name, bpc); in dce4_hdmi_set_color_depth()
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| /drivers/gpu/drm/amd/display/dc/dsc/ |
| D | rc_calc.c | 43 enum bits_per_comp bpc; in calc_rc_params() local
52 bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) in calc_rc_params()
58 _do_calc_rc_params(rc, mode, bpc, drm_bpp, is_navite_422_or_420, in calc_rc_params()
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| /drivers/video/console/ |
| D | sticon.c | 179 int size, i, bpc, pitch; in sticon_set_font() local
188 bpc = pitch * h; in sticon_set_font()
189 size = bpc * op->charcount; in sticon_set_font()
200 new_font->bytes_per_char = bpc; in sticon_set_font()
218 memcpy(p, data, bpc); in sticon_set_font()
220 p += bpc; in sticon_set_font()
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| /drivers/gpu/drm/bridge/ |
| D | tc358775.c | 273 u8 bpc; member
426 if (tc->bpc == 8) in tc_bridge_enable()
431 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; in tc_bridge_enable()
434 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; in tc_bridge_enable()
436 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / in tc_bridge_enable()
455 tc->bpc); in tc_bridge_enable()
511 tc->bpc = 8; in tc_mode_valid()
515 tc->bpc = 6; in tc_mode_valid()
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| /drivers/gpu/drm/xlnx/ |
| D | zynqmp_dp.c | 1112 unsigned int bpc) in zynqmp_dp_set_format() argument
1148 if (display->bpc && bpc > display->bpc) { in zynqmp_dp_set_format()
1151 bpc, display->bpc); in zynqmp_dp_set_format()
1152 bpc = display->bpc; in zynqmp_dp_set_format()
1157 switch (bpc) { in zynqmp_dp_set_format()
1175 bpc); in zynqmp_dp_set_format()
1177 bpc = 8; in zynqmp_dp_set_format()
1182 config->bpp = bpc * num_colors; in zynqmp_dp_set_format()
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| /drivers/gpu/drm/tegra/ |
| D | plane.c | 471 bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc) in tegra_plane_format_is_yuv() argument
479 if (bpc) in tegra_plane_format_is_yuv()
480 *bpc = 8; in tegra_plane_format_is_yuv()
495 if (bpc) in tegra_plane_format_is_yuv()
496 *bpc = 8; in tegra_plane_format_is_yuv()
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