| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hubbub.c | 253 unsigned int bpe, in hubbub3_det_request_size() argument
261 hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe); in hubbub3_det_request_size()
263 swath_bytes_horz_wc = width * blk256_height * bpe; in hubbub3_det_request_size()
264 swath_bytes_vert_wc = height * blk256_width * bpe; in hubbub3_det_request_size()
282 unsigned int bpe; in hubbub3_get_dcc_compression_cap() local
292 &bpe)) in hubbub3_get_dcc_compression_cap()
295 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, in hubbub3_get_dcc_compression_cap()
301 bpe, &req128_horz_wc, &req128_vert_wc); in hubbub3_get_dcc_compression_cap()
334 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) in hubbub3_get_dcc_compression_cap()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubbub.c | 195 unsigned int bpe, in hubbub2_det_request_size() argument
203 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe); in hubbub2_det_request_size()
205 swath_bytes_horz_wc = width * blk256_height * bpe; in hubbub2_det_request_size()
206 swath_bytes_vert_wc = height * blk256_width * bpe; in hubbub2_det_request_size()
224 unsigned int bpe; in hubbub2_get_dcc_compression_cap() local
234 &bpe)) in hubbub2_get_dcc_compression_cap()
237 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, in hubbub2_get_dcc_compression_cap()
243 bpe, &req128_horz_wc, &req128_vert_wc); in hubbub2_get_dcc_compression_cap()
276 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) in hubbub2_get_dcc_compression_cap()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubbub.c | 821 unsigned int bpe, in hubbub1_det_request_size() argument
831 hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe); in hubbub1_det_request_size()
833 swath_bytes_horz_wc = width * blk256_height * bpe; in hubbub1_det_request_size()
834 swath_bytes_vert_wc = height * blk256_width * bpe; in hubbub1_det_request_size()
854 unsigned int bpe; in hubbub1_get_dcc_compression_cap() local
863 if (!hubbub1->base.funcs->dcc_support_pixel_format(input->format, &bpe)) in hubbub1_get_dcc_compression_cap()
866 if (!hubbub1->base.funcs->dcc_support_swizzle(input->swizzle_mode, bpe, in hubbub1_get_dcc_compression_cap()
871 bpe, &req128_horz_wc, &req128_vert_wc); in hubbub1_get_dcc_compression_cap()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hubbub.c | 759 unsigned int bpe, in hubbub31_det_request_size() argument
767 hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe); in hubbub31_det_request_size()
769 swath_bytes_horz_wc = width * blk256_height * bpe; in hubbub31_det_request_size()
770 swath_bytes_vert_wc = height * blk256_width * bpe; in hubbub31_det_request_size()
787 unsigned int bpe; in hubbub31_get_dcc_compression_cap() local
797 &bpe)) in hubbub31_get_dcc_compression_cap()
800 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe, in hubbub31_get_dcc_compression_cap()
806 bpe, &req128_horz_wc, &req128_vert_wc); in hubbub31_get_dcc_compression_cap()
839 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X)) in hubbub31_get_dcc_compression_cap()
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| /drivers/gpu/drm/radeon/ |
| D | r600_cs.c | 520 u32 nviews, bpe, ntiles, slice_tile_max, tmp; in r600_cs_track_validate_db() local
536 bpe = 2; in r600_cs_track_validate_db()
543 bpe = 4; in r600_cs_track_validate_db()
546 bpe = 8; in r600_cs_track_validate_db()
558 tmp = (tmp / bpe) >> 6; in r600_cs_track_validate_db()
561 track->db_depth_size, bpe, track->db_offset, in r600_cs_track_validate_db()
581 array_check.blocksize = bpe; in r600_cs_track_validate_db()
621 tmp = ntiles * bpe * 64 * nviews * track->nsamples; in r600_cs_track_validate_db()
625 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, in r600_cs_track_validate_db()
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| D | evergreen_cs.c | 182 unsigned bpe; member
193 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; in evergreen_surface_check_linear()
194 surf->base_align = surf->bpe; in evergreen_surface_check_linear()
207 palign = MAX(64, track->group_size / surf->bpe); in evergreen_surface_check_linear_aligned()
208 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples; in evergreen_surface_check_linear_aligned()
229 palign = track->group_size / (8 * surf->bpe * surf->nsamples); in evergreen_surface_check_1d()
231 surf->layer_size = surf->nbx * surf->nby * surf->bpe; in evergreen_surface_check_1d()
239 track->group_size, surf->bpe, surf->nsamples); in evergreen_surface_check_1d()
261 tileb = 64 * surf->bpe * surf->nsamples; in evergreen_surface_check_2d()
301 surf->bpe = r600_fmt_get_blocksize(surf->format); in evergreen_surface_check()
[all …]
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 331 unsigned int bpe; in pipe_ctx_to_e2e_pipe_params() local
334 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
1017 unsigned int bpe; in dcn_validate_bandwidth() local
1020 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no; in dcn_validate_bandwidth()
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