| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn3_build_wm_range_table()
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_build_wm_range_table()
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_build_wm_range_table()
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_build_wm_range_table()
119 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn3_build_wm_range_table()
120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn3_build_wm_range_table()
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0; in dcn3_build_wm_range_table()
122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn3_build_wm_range_table()
123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn3_build_wm_range_table()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 410 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *… in dcn31_build_watermark_ranges() argument
418 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
421 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
433 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
436 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
479 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table); in dcn31_notify_wm_ranges()
550 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in dcn31_clk_mgr_helper_populate_bw_params() local
572 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
583 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 459 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ra… in build_watermark_ranges() argument
467 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
470 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
471 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
482 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
484 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
523 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
866 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks… in rn_clk_mgr_helper_populate_bw_params() argument
889 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
891 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 398 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table) in vg_build_watermark_ranges() argument
406 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
409 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
421 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
424 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
468 vg_build_watermark_ranges(clk_mgr_base->bw_params, table); in vg_notify_wm_ranges()
637 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in vg_clk_mgr_helper_populate_bw_params() local
658 bw_params->clk_table.num_entries = j + 1; in vg_clk_mgr_helper_populate_bw_params()
660 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in vg_clk_mgr_helper_populate_bw_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 1282 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn302_update_bw_bounding_box() argument
1306 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_update_bw_bounding_box()
1310 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_update_bw_bounding_box()
1311 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1312 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_update_bw_bounding_box()
1313 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_update_bw_bounding_box()
1314 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_update_bw_bounding_box()
1315 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_update_bw_bounding_box()
1316 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_update_bw_bounding_box()
1317 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_update_bw_bounding_box()
[all …]
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| D | dcn302_resource.h | 33 void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 1212 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn303_update_bw_bounding_box() argument
1236 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_update_bw_bounding_box()
1240 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_update_bw_bounding_box()
1241 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_update_bw_bounding_box()
1242 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_update_bw_bounding_box()
1243 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_update_bw_bounding_box()
1244 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_update_bw_bounding_box()
1245 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_update_bw_bounding_box()
1246 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_update_bw_bounding_box()
1247 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_update_bw_bounding_box()
[all …]
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| D | dcn303_resource.h | 15 void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 2146 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_calculate_wm_and_dlg_fp()
2151 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_calculate_wm_and_dlg_fp()
2152 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()
2153 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_calculate_wm_and_dlg_fp()
2193 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_calculate_wm_and_dlg_fp()
2198 …min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.n… in dcn30_calculate_wm_and_dlg_fp()
2202 …if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i]… in dcn30_calculate_wm_and_dlg_fp()
2205 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[… in dcn30_calculate_wm_and_dlg_fp()
2206 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_calculate_wm_and_dlg_fp()
2207 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_in… in dcn30_calculate_wm_and_dlg_fp()
[all …]
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| D | dcn30_resource.h | 97 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
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| /drivers/media/tuners/ |
| D | tda18212.c | 36 static const u8 bw_params[][3] = { in tda18212_set_params() local
115 ret = regmap_write(dev->regmap, 0x23, bw_params[i][2]); in tda18212_set_params()
123 ret = regmap_write(dev->regmap, 0x0f, bw_params[i][0]); in tda18212_set_params()
128 buf[1] = bw_params[i][1]; in tda18212_set_params()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1652 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
1653 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
1654 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
1655 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
1688 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn31_calculate_wm_and_dlg_fp()
1693 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
1694 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn31_calculate_wm_and_dlg_fp()
1695 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn31_calculate_wm_and_dlg_fp()
1714 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn31_calculate_wm_and_dlg_fp()
1715 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1072 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
1079 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
1090 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()
1107 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn21_calculate_wm() local
1109 ASSERT(bw_params); in dcn21_calculate_wm()
1152 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn21_calculate_wm()
1156 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
1164 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn21_calculate_wm()
1169 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn21_calculate_wm()
1175 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1575 static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) in dcn301_update_bw_bounding_box() argument
1578 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_update_bw_bounding_box()
1587 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_update_bw_bounding_box()
1670 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params; in dcn301_calculate_wm_and_dlg() local
1672 ASSERT(bw_params); in dcn301_calculate_wm_and_dlg()
1674 vlevel_max = bw_params->clk_table.num_entries - 1; in dcn301_calculate_wm_and_dlg()
1677 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_calculate_wm_and_dlg()
1685 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_calculate_wm_and_dlg()
1690 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_calculate_wm_and_dlg()
1696 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 280 struct clk_bw_params *bw_params; member
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| /drivers/media/dvb-frontends/ |
| D | rtl2832.c | 411 static u8 bw_params[3][32] = { in rtl2832_set_frontend() local
477 for (j = 0; j < sizeof(bw_params[0]); j++) { in rtl2832_set_frontend()
479 0x11c + j, &bw_params[i][j], 1); in rtl2832_set_frontend()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 181 struct clk_bw_params *bw_params);
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.h | 506 struct bnx2x_ets_bw_params bw_params; member
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| D | bnx2x_dcb.c | 592 ets_params.cos[i].params.bw_params.bw = in bnx2x_dcbx_update_ets_config()
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| D | bnx2x_link.c | 906 if (!ets_params->cos[cos_idx].params.bw_params.bw) { in bnx2x_ets_e3b0_get_total_bw()
912 ets_params->cos[cos_idx].params.bw_params.bw in bnx2x_ets_e3b0_get_total_bw()
916 ets_params->cos[cos_idx].params.bw_params.bw; in bnx2x_ets_e3b0_get_total_bw()
1185 ets_params->cos[cos_entry].params.bw_params.bw, in bnx2x_ets_e3b0_config()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 899 dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); in dc_construct()
|