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Searched refs:cached_state (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm_8960.c65 struct pll_28nm_cached_state cached_state; member
346 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; in dsi_28nm_pll_save_state() local
349 cached_state->postdiv3 = in dsi_28nm_pll_save_state()
351 cached_state->postdiv2 = in dsi_28nm_pll_save_state()
353 cached_state->postdiv1 = in dsi_28nm_pll_save_state()
356 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); in dsi_28nm_pll_save_state()
362 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; in dsi_28nm_pll_restore_state() local
367 cached_state->vco_rate, 0); in dsi_28nm_pll_restore_state()
375 cached_state->postdiv3); in dsi_28nm_pll_restore_state()
377 cached_state->postdiv2); in dsi_28nm_pll_restore_state()
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Ddsi_phy_28nm.c73 struct pll_28nm_cached_state cached_state; member
481 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; in dsi_28nm_pll_save_state() local
484 cached_state->postdiv3 = in dsi_28nm_pll_save_state()
486 cached_state->postdiv1 = in dsi_28nm_pll_save_state()
488 cached_state->byte_mux = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG); in dsi_28nm_pll_save_state()
490 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); in dsi_28nm_pll_save_state()
492 cached_state->vco_rate = 0; in dsi_28nm_pll_save_state()
498 struct pll_28nm_cached_state *cached_state = &pll_28nm->cached_state; in dsi_28nm_pll_restore_state() local
503 cached_state->vco_rate, 0); in dsi_28nm_pll_restore_state()
511 cached_state->postdiv3); in dsi_28nm_pll_restore_state()
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Ddsi_phy_14nm.c79 struct pll_14nm_cached_state cached_state; member
692 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; in dsi_14nm_pll_save_state() local
698 cached_state->n1postdiv = data & 0xf; in dsi_14nm_pll_save_state()
699 cached_state->n2postdiv = (data >> 4) & 0xf; in dsi_14nm_pll_save_state()
702 cached_state->n1postdiv, cached_state->n2postdiv); in dsi_14nm_pll_save_state()
704 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); in dsi_14nm_pll_save_state()
710 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; in dsi_14nm_pll_restore_state() local
716 cached_state->vco_rate, 0); in dsi_14nm_pll_restore_state()
723 data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); in dsi_14nm_pll_restore_state()
726 cached_state->n1postdiv, cached_state->n2postdiv); in dsi_14nm_pll_restore_state()
Ddsi_phy_10nm.c79 struct pll_10nm_cached_state cached_state; member
472 struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; in dsi_10nm_pll_save_state()
495 struct pll_10nm_cached_state *cached = &pll_10nm->cached_state; in dsi_10nm_pll_restore_state()
Ddsi_phy_7nm.c78 struct pll_7nm_cached_state cached_state; member
500 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; in dsi_7nm_pll_save_state()
523 struct pll_7nm_cached_state *cached = &pll_7nm->cached_state; in dsi_7nm_pll_restore_state()
/drivers/mux/
Dcore.c117 mux->cached_state = MUX_CACHE_UNKNOWN; in mux_chip_alloc()
131 mux->cached_state = ret < 0 ? MUX_CACHE_UNKNOWN : state; in mux_control_set()
155 if (mux->idle_state == mux->cached_state) in mux_chip_register()
303 if (mux->cached_state == state) in __mux_control_select()
399 mux->idle_state != mux->cached_state) in mux_control_deselect()
/drivers/iio/multiplexer/
Diio-mux.c29 int cached_state; member
47 mux->cached_state = -1; in iio_mux_select()
51 if (mux->cached_state == chan->channel) in iio_mux_select()
70 mux->cached_state = -1; in iio_mux_select()
75 mux->cached_state = chan->channel; in iio_mux_select()
393 mux->cached_state = -1; in mux_probe()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.h474 struct drm_atomic_state *cached_state; member
Damdgpu_dm.c2445 WARN_ON(adev->dm.cached_state); in dm_suspend()
2446 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev)); in dm_suspend()
2760 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) in dm_resume()
2768 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { in dm_resume()
2777 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { in dm_resume()
2786 drm_atomic_helper_resume(ddev, dm->cached_state); in dm_resume()
2788 dm->cached_state = NULL; in dm_resume()