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Searched refs:cfg_reg (Results 1 – 16 of 16) sorted by relevance

/drivers/clk/spear/
Dclk-vco-pll.c134 p = readl_relaxed(pll->vco->cfg_reg); in clk_pll_recalc_rate()
157 val = readl_relaxed(pll->vco->cfg_reg); in clk_pll_set_rate()
160 writel_relaxed(val, pll->vco->cfg_reg); in clk_pll_set_rate()
204 val = readl_relaxed(vco->cfg_reg); in clk_vco_recalc_rate()
249 val = readl_relaxed(vco->cfg_reg); in clk_vco_set_rate()
261 writel_relaxed(val, vco->cfg_reg); in clk_vco_set_rate()
278 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt, in clk_register_vco_pll()
288 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || in clk_register_vco_pll()
304 vco->cfg_reg = cfg_reg; in clk_register_vco_pll()
Dclk.h96 void __iomem *cfg_reg; member
126 *cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
/drivers/pinctrl/renesas/
Dcore.c846 const struct pinmux_cfg_reg *cfg_reg) in sh_pfc_check_cfg_reg() argument
850 sh_pfc_check_reg(drvname, cfg_reg->reg); in sh_pfc_check_cfg_reg()
852 if (cfg_reg->field_width) { in sh_pfc_check_cfg_reg()
853 fw = cfg_reg->field_width; in sh_pfc_check_cfg_reg()
854 n = (cfg_reg->reg_width / fw) << fw; in sh_pfc_check_cfg_reg()
859 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) { in sh_pfc_check_cfg_reg()
860 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) in sh_pfc_check_cfg_reg()
862 cfg_reg->reg, rw, rw + fw - 1); in sh_pfc_check_cfg_reg()
867 if (rw != cfg_reg->reg_width) in sh_pfc_check_cfg_reg()
869 cfg_reg->reg, rw, cfg_reg->reg_width); in sh_pfc_check_cfg_reg()
[all …]
/drivers/clk/
Dclk-lochnagar.c32 u16 cfg_reg; member
87 .cfg_reg = LOCHNAGAR1_##REG, \
96 .cfg_reg = LOCHNAGAR2_##ID##_CTRL, \
152 ret = regmap_update_bits(regmap, lclk->cfg_reg, in lochnagar_clk_prepare()
168 ret = regmap_update_bits(regmap, lclk->cfg_reg, lclk->ena_mask, 0); in lochnagar_clk_unprepare()
/drivers/staging/wfx/
Dbh.c226 u32 cfg_reg; in ack_sdio_data() local
228 config_reg_read(wdev, &cfg_reg); in ack_sdio_data()
229 if (cfg_reg & 0xFF) { in ack_sdio_data()
231 cfg_reg & 0xFF); in ack_sdio_data()
/drivers/net/ethernet/altera/
Daltera_tse_main.c638 u32 cfg_reg = ioread32(&priv->mac_dev->command_config); in altera_tse_adjust_link() local
644 cfg_reg |= MAC_CMDCFG_HD_ENA; in altera_tse_adjust_link()
646 cfg_reg &= ~MAC_CMDCFG_HD_ENA; in altera_tse_adjust_link()
659 cfg_reg |= MAC_CMDCFG_ETH_SPEED; in altera_tse_adjust_link()
660 cfg_reg &= ~MAC_CMDCFG_ENA_10; in altera_tse_adjust_link()
663 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; in altera_tse_adjust_link()
664 cfg_reg &= ~MAC_CMDCFG_ENA_10; in altera_tse_adjust_link()
667 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED; in altera_tse_adjust_link()
668 cfg_reg |= MAC_CMDCFG_ENA_10; in altera_tse_adjust_link()
678 iowrite32(cfg_reg, &priv->mac_dev->command_config); in altera_tse_adjust_link()
/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_component.c577 u32 __iomem *cfg_reg, in compiz_enable_input() argument
593 malidp_write32(cfg_reg, CU_INPUT0_SIZE, in compiz_enable_input()
595 malidp_write32(cfg_reg, CU_INPUT0_OFFSET, in compiz_enable_input()
597 malidp_write32(cfg_reg, CU_INPUT0_CONTROL, ctrl); in compiz_enable_input()
605 u32 __iomem *id_reg, *cfg_reg; in d71_compiz_update() local
610 cfg_reg = reg + index * CU_PER_INPUT_REGS; in d71_compiz_update()
612 compiz_enable_input(id_reg, cfg_reg, in d71_compiz_update()
617 malidp_write32(cfg_reg, CU_INPUT0_CONTROL, 0); in d71_compiz_update()
/drivers/net/ethernet/hisilicon/
Dhns_mdio.c146 u32 cfg_reg, u32 set_val, in mdio_sc_cfg_reg_write() argument
153 regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val); in mdio_sc_cfg_reg_write()
/drivers/mmc/host/
Datmel-mci.c341 u32 cfg_reg; member
1260 atmci_writel(host, ATMCI_CFG, host->cfg_reg); in atmci_start_request()
1406 atmci_writel(host, ATMCI_CFG, host->cfg_reg); in atmci_set_ios()
1458 host->cfg_reg |= ATMCI_CFG_HSMODE; in atmci_set_ios()
1460 host->cfg_reg &= ~ATMCI_CFG_HSMODE; in atmci_set_ios()
1466 atmci_writel(host, ATMCI_CFG, host->cfg_reg); in atmci_set_ios()
1576 atmci_writel(host, ATMCI_CFG, host->cfg_reg); in atmci_request_end()
1675 atmci_writel(host, ATMCI_CFG, host->cfg_reg); in atmci_detect_change()
/drivers/pinctrl/samsung/
Dpinctrl-samsung.c440 u32 cfg_value, cfg_reg; in samsung_pinconf_rw() local
452 cfg_reg = type->reg_offset[cfg_type]; in samsung_pinconf_rw()
458 data = readl(reg_base + cfg_reg); in samsung_pinconf_rw()
464 writel(data, reg_base + cfg_reg); in samsung_pinconf_rw()
/drivers/net/wireless/intel/iwlwifi/pcie/
Dtrans.c3171 u32 base, end, cfg_reg, monitor_len; in iwl_trans_get_fw_monitor_len() local
3174 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3175 cfg_reg = iwl_read_prph(trans, cfg_reg); in iwl_trans_get_fw_monitor_len()
3176 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << in iwl_trans_get_fw_monitor_len()
3182 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> in iwl_trans_get_fw_monitor_len()
/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_ethtool.c1981 int cfg_reg; in bnx2x_get_pauseparam() local
1987 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx]; in bnx2x_get_pauseparam()
1989 cfg_reg = bp->link_params.req_fc_auto_adv; in bnx2x_get_pauseparam()
1991 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) == in bnx2x_get_pauseparam()
1993 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == in bnx2x_get_pauseparam()
/drivers/net/ethernet/freescale/fman/
Dfman.c956 u32 cfg_reg = 0; in enable() local
963 cfg_reg = QMI_CFG_EN_COUNTERS; in enable()
966 cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh; in enable()
969 iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN, in enable()
/drivers/net/wireless/intel/iwlwifi/fw/
Dfile.h644 __le32 cfg_reg; member
/drivers/net/wireless/intel/iwlwifi/
Diwl-drv.c1454 dest_tlv->base_reg = pieces->dbg_dest_tlv->cfg_reg; in iwl_req_fw_callback()
/drivers/misc/habanalabs/goya/
Dgoya.c1134 static int goya_stop_queue(struct hl_device *hdev, u32 cfg_reg, in goya_stop_queue() argument
1142 WREG32(cfg_reg, 1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT); in goya_stop_queue()