/drivers/gpu/drm/radeon/ |
D | r600_dpm.h | 133 void r600_dpm_print_class_info(u32 class, u32 class2); 139 bool r600_is_uvd_state(u32 class, u32 class2);
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D | r600_dpm.c | 69 void r600_dpm_print_class_info(u32 class, u32 class2) in r600_dpm_print_class_info() argument 92 (class2 == 0)) in r600_dpm_print_class_info() 121 if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) in r600_dpm_print_class_info() 123 if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in r600_dpm_print_class_info() 125 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in r600_dpm_print_class_info() 724 bool r600_is_uvd_state(u32 class, u32 class2) in r600_is_uvd_state() argument 734 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in r600_is_uvd_state()
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D | rs780_dpm.c | 724 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rs780_parse_pplib_non_clock_info() 734 if (r600_is_uvd_state(rps->class, rps->class2)) { in rs780_parse_pplib_non_clock_info() 943 r600_dpm_print_class_info(rps->class, rps->class2); in rs780_dpm_print_power_state()
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D | sumo_dpm.c | 828 !r600_is_uvd_state(new_rps->class, new_rps->class2)) in sumo_setup_uvd_clocks() 1142 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)) in sumo_apply_state_adjust_rules() 1411 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in sumo_parse_pplib_non_clock_info() 1802 r600_dpm_print_class_info(rps->class, rps->class2); in sumo_dpm_print_power_state()
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D | trinity_dpm.c | 1434 if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) { in trinity_adjust_uvd_state() 1645 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in trinity_parse_pplib_non_clock_info() 1975 r600_dpm_print_class_info(rps->class, rps->class2); in trinity_dpm_print_power_state()
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D | rv770_dpm.c | 2152 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rv7xx_parse_pplib_non_clock_info() 2162 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv7xx_parse_pplib_non_clock_info() 2236 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { in rv7xx_parse_pplib_clock_info() 2440 r600_dpm_print_class_info(rps->class, rps->class2); in rv770_dpm_print_power_state()
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D | ni_dpm.c | 2608 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) { in ni_enable_power_containment() 3390 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) { in ni_enable_smc_cac() 3904 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in ni_parse_pplib_non_clock_info() 3909 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in ni_parse_pplib_non_clock_info() 3958 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { in ni_parse_pplib_clock_info() 4292 r600_dpm_print_class_info(rps->class, rps->class2); in ni_dpm_print_power_state()
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D | rv6xx_dpm.c | 1800 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rv6xx_parse_pplib_non_clock_info() 1802 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv6xx_parse_pplib_non_clock_info() 2013 r600_dpm_print_class_info(rps->class, rps->class2); in rv6xx_dpm_print_power_state()
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D | btc_dpm.c | 1696 if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) in btc_set_at_for_uvd() 1718 if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) { in btc_notify_uvd_to_smc()
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D | radeon_pm.c | 997 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in radeon_dpm_pick_power_state() 1011 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in radeon_dpm_pick_power_state()
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D | kv_dpm.c | 2389 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in kv_parse_pplib_non_clock_info() 2651 r600_dpm_print_class_info(rps->class, rps->class2); in kv_dpm_print_power_state()
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D | si_dpm.c | 6693 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in si_parse_pplib_non_clock_info() 6698 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info() 6751 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && in si_parse_pplib_clock_info()
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D | ci_dpm.c | 5422 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in ci_parse_pplib_non_clock_info() 5465 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) { in ci_parse_pplib_clock_info() 5938 r600_dpm_print_class_info(rps->class, rps->class2); in ci_dpm_print_power_state()
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D | radeon.h | 1372 u32 class2; /* vbios flags */ member
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/drivers/gpu/drm/amd/pm/ |
D | amdgpu_dpm.c | 37 void amdgpu_dpm_print_class_info(u32 class, u32 class2) in amdgpu_dpm_print_class_info() argument 59 (class2 == 0)) in amdgpu_dpm_print_class_info() 88 if (class2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) in amdgpu_dpm_print_class_info() 90 if (class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in amdgpu_dpm_print_class_info() 92 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in amdgpu_dpm_print_class_info() 1361 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in amdgpu_dpm_pick_power_state() 1375 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) in amdgpu_dpm_pick_power_state()
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/drivers/gpu/drm/amd/pm/inc/ |
D | amdgpu_dpm.h | 58 u32 class2; /* vbios flags */ member 494 void amdgpu_dpm_print_class_info(u32 class, u32 class2);
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/drivers/scsi/bfa/ |
D | bfa_fc.h | 351 struct fc_plogi_clp_s class2; /* class 2 service parameters */ member
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D | bfa_fcs_rport.c | 2534 if (plogi->class2.class_valid) in bfa_fcs_rport_update()
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/drivers/gpu/drm/amd/pm/powerplay/ |
D | si_dpm.c | 3359 static bool r600_is_uvd_state(u32 class, u32 class2) in r600_is_uvd_state() argument 3369 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) in r600_is_uvd_state() 7110 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in si_parse_pplib_non_clock_info() 7115 } else if (r600_is_uvd_state(rps->class, rps->class2)) { in si_parse_pplib_non_clock_info() 7168 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && in si_parse_pplib_clock_info() 7897 amdgpu_dpm_print_class_info(rps->class, rps->class2); in si_dpm_print_power_state()
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D | kv_dpm.c | 2647 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in kv_parse_pplib_non_clock_info() 2883 amdgpu_dpm_print_class_info(rps->class, rps->class2); in kv_dpm_print_power_state()
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