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Searched refs:csc (Results 1 – 25 of 58) sorted by relevance

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/drivers/gpu/ipu-v3/
Dipu-ic-csc.c355 static int calc_csc_coeffs(struct ipu_ic_csc *csc) in calc_csc_coeffs() argument
360 tbl_idx = (QUANT_MAP(csc->in_cs.quant) << 1) | in calc_csc_coeffs()
361 QUANT_MAP(csc->out_cs.quant); in calc_csc_coeffs()
363 if (csc->in_cs.cs == csc->out_cs.cs) { in calc_csc_coeffs()
364 csc->params = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
372 switch (csc->out_cs.enc) { in calc_csc_coeffs()
374 params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
378 params_tbl = (csc->in_cs.cs == IPUV3_COLORSPACE_YUV) ? in calc_csc_coeffs()
385 csc->params = *params_tbl[tbl_idx]; in calc_csc_coeffs()
390 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc) in __ipu_ic_calc_csc() argument
[all …]
Dipu-ic.c175 const struct ipu_ic_csc *csc, in init_csc() argument
188 c = (const u16 (*)[3])csc->params.coeff; in init_csc()
189 a = (const u16 *)csc->params.offset; in init_csc()
195 param = ((a[0] & 0x1fe0) >> 5) | (csc->params.scale << 8) | in init_csc()
196 (csc->params.sat << 10); in init_csc()
398 const struct ipu_ic_csc *csc, in ipu_ic_task_init_rsc() argument
432 ic->in_cs = csc->in_cs; in ipu_ic_task_init_rsc()
433 ic->out_cs = csc->out_cs; in ipu_ic_task_init_rsc()
435 ret = init_csc(ic, csc, 0); in ipu_ic_task_init_rsc()
442 const struct ipu_ic_csc *csc, in ipu_ic_task_init() argument
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Dipu-dp.c273 u32 reg, csc; in ipu_dp_disable_channel() local
283 csc = reg & DP_COM_CONF_CSC_DEF_MASK; in ipu_dp_disable_channel()
285 if (csc == DP_COM_CONF_CSC_DEF_BOTH || csc == DP_COM_CONF_CSC_DEF_BG) in ipu_dp_disable_channel()
/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/
Dia_css_csc.host.c69 const struct sh_css_isp_csc_params *csc, in ia_css_cc_dump() argument
73 if (!csc) return; in ia_css_cc_dump()
77 csc->m_shift); in ia_css_cc_dump()
80 csc->m00); in ia_css_cc_dump()
83 csc->m01); in ia_css_cc_dump()
86 csc->m02); in ia_css_cc_dump()
89 csc->m10); in ia_css_cc_dump()
92 csc->m11); in ia_css_cc_dump()
95 csc->m12); in ia_css_cc_dump()
98 csc->m20); in ia_css_cc_dump()
[all …]
Dia_css_csc.host.h39 const struct sh_css_isp_csc_params *csc, unsigned int level,
44 const struct sh_css_isp_csc_params *csc,
/drivers/media/platform/ti-vpe/
Dcsc.c110 void csc_dump_regs(struct csc_data *csc) in csc_dump_regs() argument
112 struct device *dev = &csc->pdev->dev; in csc_dump_regs()
115 ioread32(csc->base + CSC_##r)) in csc_dump_regs()
117 dev_dbg(dev, "CSC Registers @ %pa:\n", &csc->res->start); in csc_dump_regs()
130 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5) in csc_set_coeff_bypass() argument
139 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0, in csc_set_coeff() argument
249 struct csc_data *csc; in csc_create() local
253 csc = devm_kzalloc(&pdev->dev, sizeof(*csc), GFP_KERNEL); in csc_create()
254 if (!csc) { in csc_create()
259 csc->pdev = pdev; in csc_create()
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DMakefile5 obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o
10 ti-csc-y := csc.o
Dcsc.h58 void csc_dump_regs(struct csc_data *csc);
59 void csc_set_coeff_bypass(struct csc_data *csc, u32 *csc_reg5);
60 void csc_set_coeff(struct csc_data *csc, u32 *csc_reg0,
/drivers/gpu/drm/tidss/
Dtidss_dispc.c1325 void (*to_regval)(const struct dispc_csc_coef *csc, u32 *regval);
1336 void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) in dispc_csc_offset_regval() argument
1339 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1340 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1341 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1347 void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regval) in dispc_csc_yuv2rgb_regval() argument
1349 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1350 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1351 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
1352 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); in dispc_csc_yuv2rgb_regval()
[all …]
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_plane.c181 enum mdp4_pipe pipe, struct csc_cfg *csc) in mdp4_write_csc_config() argument
185 for (i = 0; i < ARRAY_SIZE(csc->matrix); i++) { in mdp4_write_csc_config()
187 csc->matrix[i]); in mdp4_write_csc_config()
190 for (i = 0; i < ARRAY_SIZE(csc->post_bias) ; i++) { in mdp4_write_csc_config()
192 csc->pre_bias[i]); in mdp4_write_csc_config()
195 csc->post_bias[i]); in mdp4_write_csc_config()
198 for (i = 0; i < ARRAY_SIZE(csc->post_clamp) ; i++) { in mdp4_write_csc_config()
200 csc->pre_clamp[i]); in mdp4_write_csc_config()
203 csc->post_clamp[i]); in mdp4_write_csc_config()
336 struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB); in mdp4_plane_mode_set() local
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/drivers/pcmcia/
Di82092.c309 int csc; in i82092aa_interrupt() local
316 csc = indirect_read(i, I365_CSC); in i82092aa_interrupt()
318 if (csc == 0) /* no events on this socket */ in i82092aa_interrupt()
323 if (csc & I365_CSC_DETECT) { in i82092aa_interrupt()
331 if (csc & I365_CSC_STSCHG) in i82092aa_interrupt()
335 if (csc & I365_CSC_BVD1) in i82092aa_interrupt()
337 if (csc & I365_CSC_BVD2) in i82092aa_interrupt()
339 if (csc & I365_CSC_READY) in i82092aa_interrupt()
Dpd6729.c192 unsigned int csc; in pd6729_interrupt() local
195 csc = indirect_read(&socket[i], I365_CSC); in pd6729_interrupt()
196 if (csc == 0) /* no events on this socket */ in pd6729_interrupt()
202 if (csc & I365_CSC_DETECT) { in pd6729_interrupt()
211 events |= (csc & I365_CSC_STSCHG) in pd6729_interrupt()
215 events |= (csc & I365_CSC_BVD1) in pd6729_interrupt()
217 events |= (csc & I365_CSC_BVD2) in pd6729_interrupt()
219 events |= (csc & I365_CSC_READY) in pd6729_interrupt()
Dvrc4171_card.c481 uint8_t status, csc; in get_events() local
484 csc = exca_read_byte(slot, I365_CSC); in get_events()
487 if ((csc & I365_CSC_STSCHG) && (status & I365_CS_STSCHG)) in get_events()
490 if (csc & (I365_CSC_BVD1 | I365_CSC_BVD2)) { in get_events()
497 if ((csc & I365_CSC_READY) && (status & I365_CS_READY)) in get_events()
499 if ((csc & I365_CSC_DETECT) && ((status & I365_CS_DETECT) == I365_CS_DETECT)) in get_events()
Dyenta_socket.c510 u8 csc; in yenta_interrupt() local
517 csc = exca_readb(socket, I365_CSC); in yenta_interrupt()
519 if (!(cb_event || csc)) in yenta_interrupt()
523 events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0; in yenta_interrupt()
525 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; in yenta_interrupt()
527 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; in yenta_interrupt()
528 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; in yenta_interrupt()
529 events |= (csc & I365_CSC_READY) ? SS_READY : 0; in yenta_interrupt()
967 u8 csc; in yenta_probe_handler() local
973 csc = exca_readb(socket, I365_CSC); in yenta_probe_handler()
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Di82365.c833 int i, j, csc; in pcic_interrupt() local
847 csc = i365_get(i, I365_CSC); in pcic_interrupt()
848 if ((csc == 0) || (i365_get(i, I365_IDENT) & 0x70)) { in pcic_interrupt()
852 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0; in pcic_interrupt()
855 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0; in pcic_interrupt()
857 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0; in pcic_interrupt()
858 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0; in pcic_interrupt()
859 events |= (csc & I365_CSC_READY) ? SS_READY : 0; in pcic_interrupt()
/drivers/gpu/drm/nouveau/dispnv50/
Dwndw.c134 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
162 if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); in nv50_wndw_flush_set()
422 if (wndw->func->csc && asyh->state.ctm) { in nv50_wndw_atomic_check_lut()
424 wndw->func->csc(wndw, asyw, ctm); in nv50_wndw_atomic_check_lut()
425 asyw->csc.valid = true; in nv50_wndw_atomic_check_lut()
426 asyw->set.csc = true; in nv50_wndw_atomic_check_lut()
428 asyw->csc.valid = false; in nv50_wndw_atomic_check_lut()
429 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
510 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check()
606 asyw->csc = armw->csc; in nv50_wndw_atomic_duplicate_state()
Dbase907c.c148 u32 *val = &asyw->csc.matrix[j * 4 + i]; in base907c_csc()
185 NVVAL(NV907C, SET_CSC_RED2RED, COEFF, asyw->csc.matrix[0]), in base907c_csc_set()
187 SET_CSC_GRN2RED, &asyw->csc.matrix[1], 11); in base907c_csc_set()
202 .csc = base907c_csc,
Datom.h212 } csc; member
258 bool csc:1; member
/drivers/media/platform/atmel/
Datmel-sama5d2-isc.c195 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama5d2_config_csc()
197 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama5d2_config_csc()
199 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama5d2_config_csc()
201 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama5d2_config_csc()
203 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama5d2_config_csc()
205 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama5d2_config_csc()
439 isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; in atmel_isc_probe()
Datmel-sama7g5-isc.c212 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, in isc_sama7g5_config_csc()
214 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, in isc_sama7g5_config_csc()
216 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, in isc_sama7g5_config_csc()
218 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, in isc_sama7g5_config_csc()
220 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, in isc_sama7g5_config_csc()
222 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, in isc_sama7g5_config_csc()
432 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; in microchip_xisc_probe()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_plane.c514 struct csc_cfg *csc) in csc_enable() argument
519 if (unlikely(!csc)) in csc_enable()
522 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type)) in csc_enable()
524 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type)) in csc_enable()
529 matrix = csc->matrix; in csc_enable()
545 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) { in csc_enable()
546 uint32_t *pre_clamp = csc->pre_clamp; in csc_enable()
547 uint32_t *post_clamp = csc->post_clamp; in csc_enable()
558 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i])); in csc_enable()
561 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i])); in csc_enable()
/drivers/media/platform/omap3isp/
Disppreview.c400 const struct omap3isp_prev_csc *csc = &params->csc; in preview_config_csc() local
403 val = (csc->matrix[0][0] & 0x3ff) << ISPPRV_CSC0_RY_SHIFT; in preview_config_csc()
404 val |= (csc->matrix[0][1] & 0x3ff) << ISPPRV_CSC0_GY_SHIFT; in preview_config_csc()
405 val |= (csc->matrix[0][2] & 0x3ff) << ISPPRV_CSC0_BY_SHIFT; in preview_config_csc()
408 val = (csc->matrix[1][0] & 0x3ff) << ISPPRV_CSC1_RCB_SHIFT; in preview_config_csc()
409 val |= (csc->matrix[1][1] & 0x3ff) << ISPPRV_CSC1_GCB_SHIFT; in preview_config_csc()
410 val |= (csc->matrix[1][2] & 0x3ff) << ISPPRV_CSC1_BCB_SHIFT; in preview_config_csc()
413 val = (csc->matrix[2][0] & 0x3ff) << ISPPRV_CSC2_RCR_SHIFT; in preview_config_csc()
414 val |= (csc->matrix[2][1] & 0x3ff) << ISPPRV_CSC2_GCR_SHIFT; in preview_config_csc()
415 val |= (csc->matrix[2][2] & 0x3ff) << ISPPRV_CSC2_BCR_SHIFT; in preview_config_csc()
[all …]
/drivers/media/platform/davinci/
Ddm355_ccdc.c451 static void ccdc_config_csc(struct ccdc_csc *csc) in ccdc_config_csc() argument
456 if (!csc->enable) in ccdc_config_csc()
466 val1 = (csc->coeff[i].integer & in ccdc_config_csc()
473 val1 |= (((csc->coeff[i].decimal & in ccdc_config_csc()
479 val2 = (csc->coeff[i].integer & in ccdc_config_csc()
482 val2 |= (((csc->coeff[i].decimal & in ccdc_config_csc()
602 ccdc_config_csc(&config_params->csc); in ccdc_config_raw()
/drivers/gpu/drm/zte/
Dzx_plane.c365 void __iomem *csc = zplane->csc; in zx_gl_plane_atomic_update() local
423 zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK, in zx_gl_plane_atomic_update()
426 zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK, in zx_gl_plane_atomic_update()
428 zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, CSC_WORK_ENABLE); in zx_gl_plane_atomic_update()
Dzx_vou.c238 void __iomem *csc = zcrtc->chncsc; in vou_inf_enable() local
244 zx_writel_mask(csc + CSC_CTRL0, CSC_COV_MODE_MASK, in vou_inf_enable()
246 zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, in vou_inf_enable()
253 zx_writel_mask(csc + CSC_CTRL0, CSC_WORK_ENABLE, 0); in vou_inf_enable()
554 zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET; in zx_crtc_init()
565 zplane->csc = vou->osd + AUX_GL_CSC_OFFSET; in zx_crtc_init()

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