Home
last modified time | relevance | path

Searched refs:csr (Results 1 – 25 of 114) sorted by relevance

12345

/drivers/usb/musb/
Dmusb_gadget.c229 u16 fifo_count = 0, csr; in txstate() local
248 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
256 musb_ep->end_point.name, csr); in txstate()
260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
262 musb_ep->end_point.name, csr); in txstate()
268 csr); in txstate()
301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
303 musb_writew(epio, MUSB_TXCSR, csr in txstate()
305 csr &= ~MUSB_TXCSR_DMAMODE; in txstate()
[all …]
Dmusb_gadget_ep0.c243 u16 csr; in service_zero_data_request() local
266 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request()
267 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request()
269 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request()
272 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request()
274 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request()
275 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request()
277 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request()
279 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request()
403 u16 csr; in service_zero_data_request() local
[all …]
Dmusb_host.c90 u16 csr; in musb_h_tx_flush_fifo() local
93 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; in musb_h_tx_flush_fifo()
96 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
97 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
115 ep->epnum, csr)) in musb_h_tx_flush_fifo()
124 u16 csr; in musb_h_ep0_flush_fifo() local
129 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()
[all …]
Dmusb_cppi41.c56 u16 csr; in save_rx_toggle() local
64 csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR); in save_rx_toggle()
65 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in save_rx_toggle()
74 u16 csr; in update_rx_toggle() local
83 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in update_rx_toggle()
84 toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0; in update_rx_toggle()
92 csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE; in update_rx_toggle()
93 musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr); in update_rx_toggle()
105 u16 csr; in musb_is_tx_fifo_empty() local
108 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty()
[all …]
Dmusbhsdma.c152 u16 csr = 0; in configure_channel() local
158 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; in configure_channel()
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
164 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) in configure_channel()
178 csr); in configure_channel()
228 u16 csr; in dma_channel_abort() local
239 csr = musb_readw(mbase, offset); in dma_channel_abort()
240 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in dma_channel_abort()
241 musb_writew(mbase, offset, csr); in dma_channel_abort()
242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
[all …]
/drivers/scsi/
Dsun3_scsi.c73 unsigned short csr; /* control/status reg */ member
196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr()
206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr()
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
242 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup()
243 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
248 dregs->csr |= CSR_SEND; in sun3scsi_dma_setup()
[all …]
Dsun3x_esp.c86 u32 csr; in sun3x_esp_dma_drain() local
89 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
90 if (!(csr & DMA_FIFO_ISDRAIN)) in sun3x_esp_dma_drain()
93 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sun3x_esp_dma_drain()
131 u32 csr; in sun3x_esp_send_dma_cmd() local
137 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
138 csr |= DMA_ENABLE; in sun3x_esp_send_dma_cmd()
140 csr |= DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
142 csr &= ~DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
143 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
[all …]
Dsun_esp.c322 u32 csr; in sbus_esp_dma_drain() local
328 csr = dma_read32(DMA_CSR); in sbus_esp_dma_drain()
329 if (!(csr & DMA_FIFO_ISDRAIN)) in sbus_esp_dma_drain()
333 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR); in sbus_esp_dma_drain()
388 u32 csr; in sbus_esp_send_dma_cmd() local
400 csr = esp->prev_hme_dmacsr; in sbus_esp_send_dma_cmd()
401 csr |= DMA_SCSI_DISAB | DMA_ENABLE; in sbus_esp_send_dma_cmd()
403 csr |= DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
405 csr &= ~DMA_ST_WRITE; in sbus_esp_send_dma_cmd()
406 esp->prev_hme_dmacsr = csr; in sbus_esp_send_dma_cmd()
[all …]
/drivers/watchdog/
Dshwdt.c85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
[all …]
/drivers/usb/gadget/udc/
Dat91_udc.c111 u32 csr; in proc_ep_show() local
118 csr = __raw_readl(ep->creg); in proc_ep_show()
132 csr, in proc_ep_show()
133 (csr & 0x07ff0000) >> 16, in proc_ep_show()
134 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
135 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
136 types[(csr & 0x700) >> 8], in proc_ep_show()
139 (!(csr & 0x700)) in proc_ep_show()
140 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
142 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
[all …]
/drivers/crypto/qat/qat_common/
Dicp_qat_hal.h125 #define SET_CAP_CSR(handle, csr, val) \ argument
126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \ argument
128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
Dadf_hw_arbiter.c21 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
36 WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg); in adf_init_arb()
42 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]); in adf_init_arb()
79 void __iomem *csr; in adf_exit_arb() local
89 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
95 WRITE_CSR_ARB_SARCONFIG(csr, arb_off, i, 0); in adf_exit_arb()
99 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, 0); in adf_exit_arb()
103 csr_ops->write_csr_ring_srv_arb_en(csr, i, 0); in adf_exit_arb()
Dadf_transport_debug.c46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show() local
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
156 void __iomem *csr = bank->csr_addr; in adf_bank_show() local
162 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_bank_show()
164 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_bank_show()
166 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_bank_show()
Dqat_hal.c77 unsigned char ae, unsigned int csr) in qat_hal_rd_ae_csr() argument
83 value = GET_AE_CSR(handle, ae, csr); in qat_hal_rd_ae_csr()
93 unsigned char ae, unsigned int csr, in qat_hal_wr_ae_csr() argument
99 SET_AE_CSR(handle, ae, csr, value); in qat_hal_wr_ae_csr()
125 unsigned int csr = (1 << ACS_ABO_BITPOS); in qat_hal_wait_cycles() local
133 csr = qat_hal_rd_ae_csr(handle, ae, ACTIVE_CTX_STATUS); in qat_hal_wait_cycles()
143 if (elapsed_cycles >= 8 && !(csr & (1 << ACS_ABO_BITPOS))) in qat_hal_wait_cycles()
159 unsigned int csr, new_csr; in qat_hal_set_ae_ctx_mode() local
167 csr = qat_hal_rd_ae_csr(handle, ae, CTX_ENABLES); in qat_hal_set_ae_ctx_mode()
168 csr = IGNORE_W1C_MASK & csr; in qat_hal_set_ae_ctx_mode()
[all …]
/drivers/pcmcia/
Dpxa2xx_sharpsl.c58 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
66 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
67 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
75 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
80 SCOOP_DEV[skt->nr].keep_vs = (csr & 0x00C0); in sharpsl_pcmcia_socket_state()
91 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
92 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
93 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
94 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
95 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
[all …]
/drivers/usb/mtu3/
Dmtu3_gadget_ep0.c139 u32 csr; in ep0_stall_set() local
142 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_stall_set()
144 csr |= EP0_SENDSTALL | pktrdy; in ep0_stall_set()
146 csr = (csr & ~EP0_SENDSTALL) | EP0_SENTSTALL; in ep0_stall_set()
147 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); in ep0_stall_set()
515 u32 csr; in ep0_rx_state() local
520 csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; in ep0_rx_state()
537 csr |= EP0_RXPKTRDY; in ep0_rx_state()
545 csr |= EP0_DATAEND; in ep0_rx_state()
550 csr |= EP0_RXPKTRDY | EP0_SENDSTALL; in ep0_rx_state()
[all …]
/drivers/crypto/qat/qat_c62x/
Dadf_c62x_hw_data.c122 void __iomem *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
127 val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
129 ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
130 val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
132 ADF_CSR_WR(csr, ADF_C62X_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
137 val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); in adf_enable_error_correction()
139 ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); in adf_enable_error_correction()
140 val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i)); in adf_enable_error_correction()
142 ADF_CSR_WR(csr, ADF_C62X_CERRSSMSH(i), val); in adf_enable_error_correction()
/drivers/crypto/qat/qat_c3xxx/
Dadf_c3xxx_hw_data.c120 void __iomem *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
125 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
127 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
128 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
130 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
135 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); in adf_enable_error_correction()
137 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); in adf_enable_error_correction()
138 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i)); in adf_enable_error_correction()
140 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val); in adf_enable_error_correction()
/drivers/crypto/qat/qat_4xxx/
Dadf_4xxx_hw_data.c88 void __iomem *csr; in set_msix_default_rttable() local
91 csr = (&GET_BARS(accel_dev)[ADF_4XXX_PMISC_BAR])->virt_addr; in set_msix_default_rttable()
93 ADF_CSR_WR(csr, ADF_4XXX_MSIX_RTTABLE_OFFSET(i), i); in set_msix_default_rttable()
145 void __iomem *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
148 ADF_CSR_WR(csr, ADF_4XXX_ERRMSK3, ADF_4XXX_VFLNOTIFY); in adf_enable_error_correction()
169 u32 csr; in adf_init_device() local
175 csr = ADF_CSR_RD(addr, ADF_4XXX_ERRMSK2); in adf_init_device()
176 csr |= ADF_4XXX_PM_SOU; in adf_init_device()
177 ADF_CSR_WR(addr, ADF_4XXX_ERRMSK2, csr); in adf_init_device()
/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c149 void __iomem *csr = misc_bar->virt_addr; in adf_enable_error_correction() local
154 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); in adf_enable_error_correction()
156 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
157 val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i)); in adf_enable_error_correction()
159 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
164 val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); in adf_enable_error_correction()
166 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
167 val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i)); in adf_enable_error_correction()
169 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
/drivers/net/wireless/ath/wil6210/
Dinterrupt.c293 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
355 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
406 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
452 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
508 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
540 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
683 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
686 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
691 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
694 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
[all …]
/drivers/power/reset/
Dxgene-reboot.c25 void *csr; member
38 writel(ctx->mask, ctx->csr); in xgene_restart_handler()
57 ctx->csr = of_iomap(dev->of_node, 0); in xgene_reboot_probe()
58 if (!ctx->csr) { in xgene_reboot_probe()
71 iounmap(ctx->csr); in xgene_reboot_probe()
/drivers/ipack/devices/
Dipoctal.c344 iowrite8(TX_CLK_9600 | RX_CLK_9600, &channel->regs->w.csr); in ipoctal_inst_slot()
505 unsigned char csr = 0; in ipoctal_set_termios() local
577 csr |= TX_CLK_75 | RX_CLK_75; in ipoctal_set_termios()
580 csr |= TX_CLK_110 | RX_CLK_110; in ipoctal_set_termios()
583 csr |= TX_CLK_150 | RX_CLK_150; in ipoctal_set_termios()
586 csr |= TX_CLK_300 | RX_CLK_300; in ipoctal_set_termios()
589 csr |= TX_CLK_600 | RX_CLK_600; in ipoctal_set_termios()
592 csr |= TX_CLK_1200 | RX_CLK_1200; in ipoctal_set_termios()
595 csr |= TX_CLK_1800 | RX_CLK_1800; in ipoctal_set_termios()
598 csr |= TX_CLK_2000 | RX_CLK_2000; in ipoctal_set_termios()
[all …]
/drivers/mtd/devices/
Dms02-nv.c188 mp->resource.csr = csr_res; in ms02nv_init_one()
255 release_resource(mp->resource.csr); in ms02nv_remove_one()
256 kfree(mp->resource.csr); in ms02nv_remove_one()
270 volatile u32 *csr; in ms02nv_init() local
277 csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); in ms02nv_init()
278 if (*csr & KN02_CSR_BNK32M) in ms02nv_init()
283 csr = (volatile u32 *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in ms02nv_init()
284 if (*csr & KN03_MCR_BNK32M) in ms02nv_init()
/drivers/edac/
Dedac_mc.c236 struct csrow_info *csr; in mci_release() local
247 csr = mci->csrows[row]; in mci_release()
248 if (!csr) in mci_release()
251 if (csr->channels) { in mci_release()
253 kfree(csr->channels[chn]); in mci_release()
254 kfree(csr->channels); in mci_release()
256 kfree(csr); in mci_release()
277 struct csrow_info *csr; in edac_mc_alloc_csrows() local
279 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); in edac_mc_alloc_csrows()
280 if (!csr) in edac_mc_alloc_csrows()
[all …]

12345