Home
last modified time | relevance | path

Searched refs:dbi_base (Results 1 – 17 of 17) sorted by relevance

/drivers/pci/controller/dwc/
Dpci-layerscape.c61 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_is_bridge()
72 iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE); in ls_pcie_clear_multifunction()
81 val = ioread32(pci->dbi_base + PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
83 iowrite32(val, pci->dbi_base + PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
123 iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); in ls_pcie_fix_error_response()
240 struct resource *dbi_base; in ls_pcie_probe() local
258 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_probe()
259 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); in ls_pcie_probe()
260 if (IS_ERR(pci->dbi_base)) in ls_pcie_probe()
261 return PTR_ERR(pci->dbi_base); in ls_pcie_probe()
[all …]
Dpci-layerscape-ep.c57 return ioread32be(pci->dbi_base + offset); in ls_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_lut_readl()
67 iowrite32be(value, pci->dbi_base + offset); in ls_lut_writel()
69 iowrite32(value, pci->dbi_base + offset); in ls_lut_writel()
231 struct resource *dbi_base; in ls_pcie_ep_probe() local
258 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_ep_probe()
259 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base); in ls_pcie_ep_probe()
260 if (IS_ERR(pci->dbi_base)) in ls_pcie_ep_probe()
261 return PTR_ERR(pci->dbi_base); in ls_pcie_ep_probe()
Dpcie-al.c19 void __iomem *dbi_base; member
27 void __iomem *dbi_base = pcie->dbi_base; in al_pcie_map_bus() local
37 return dbi_base + where; in al_pcie_map_bus()
69 al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res); in al_pcie_init()
70 if (IS_ERR(al_pcie->dbi_base)) in al_pcie_init()
71 return PTR_ERR(al_pcie->dbi_base); in al_pcie_init()
Dpcie-tegra194-acpi.c19 void __iomem *dbi_base; member
33 pcie_ecam->dbi_base = cfg->win + SZ_512K; in tegra194_acpi_init()
78 return pcie_ecam->dbi_base + where; in tegra194_map_bus()
Dpcie-designware.c153 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
155 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
168 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
172 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
559 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); in dw_pcie_link_up()
702 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_iatu_detect()
Dpcie-armada8k.c309 pci->dbi_base = devm_pci_remap_cfg_resource(dev, base); in armada8k_pcie_probe()
310 if (IS_ERR(pci->dbi_base)) { in armada8k_pcie_probe()
311 ret = PTR_ERR(pci->dbi_base); in armada8k_pcie_probe()
Dpci-dra7xx.c453 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics"); in dra7xx_add_pcie_ep()
454 if (IS_ERR(pci->dbi_base)) in dra7xx_add_pcie_ep()
455 return PTR_ERR(pci->dbi_base); in dra7xx_add_pcie_ep()
490 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics"); in dra7xx_add_pcie_port()
491 if (IS_ERR(pci->dbi_base)) in dra7xx_add_pcie_port()
492 return PTR_ERR(pci->dbi_base); in dra7xx_add_pcie_port()
Dpcie-designware-host.c308 if (!pci->dbi_base) { in dw_pcie_host_init()
310 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res); in dw_pcie_host_init()
311 if (IS_ERR(pci->dbi_base)) in dw_pcie_host_init()
312 return PTR_ERR(pci->dbi_base); in dw_pcie_host_init()
531 return pci->dbi_base + where; in dw_pcie_own_conf_map_bus()
Dpci-imx6.c986 struct resource *dbi_base; in imx6_pcie_probe() local
1021 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); in imx6_pcie_probe()
1022 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); in imx6_pcie_probe()
1023 if (IS_ERR(pci->dbi_base)) in imx6_pcie_probe()
1024 return PTR_ERR(pci->dbi_base); in imx6_pcie_probe()
1075 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) in imx6_pcie_probe()
Dpcie-histb.c328 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc-dbi"); in histb_pcie_probe()
329 if (IS_ERR(pci->dbi_base)) { in histb_pcie_probe()
331 return PTR_ERR(pci->dbi_base); in histb_pcie_probe()
Dpcie-qcom.c412 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); in qcom_pcie_init_2_1_0()
414 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); in qcom_pcie_init_2_1_0()
1126 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); in qcom_pcie_post_init_2_3_3()
1127 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); in qcom_pcie_post_init_2_3_3()
1128 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); in qcom_pcie_post_init_2_3_3()
1130 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
1132 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); in qcom_pcie_post_init_2_3_3()
1134 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + in qcom_pcie_post_init_2_3_3()
1271 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); in qcom_pcie_link_up()
Dpci-meson.c113 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); in meson_pcie_get_mems()
114 if (IS_ERR(pci->dbi_base)) in meson_pcie_get_mems()
115 return PTR_ERR(pci->dbi_base); in meson_pcie_get_mems()
Dpcie-designware-ep.c689 if (!pci->dbi_base) { in dw_pcie_ep_init()
691 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); in dw_pcie_ep_init()
692 if (IS_ERR(pci->dbi_base)) in dw_pcie_ep_init()
693 return PTR_ERR(pci->dbi_base); in dw_pcie_ep_init()
699 pci->dbi_base2 = pci->dbi_base + SZ_4K; in dw_pcie_ep_init()
Dpcie-intel-gw.c110 pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
304 pci->atu_base = pci->dbi_base + 0xC0000; in intel_pcie_host_setup()
Dpcie-spear13xx.c131 spear13xx_pcie->app_base = pci->dbi_base + 0x2000; in spear13xx_pcie_host_init()
Dpcie-designware.h261 void __iomem *dbi_base; member
Dpci-keystone.c816 pci->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
1140 pci->dbi_base = base; in ks_pcie_probe()