| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_surface.c | 40 static void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state) in dc_plane_construct()
66 static void dc_plane_destruct(struct dc_plane_state *plane_state) in dc_plane_destruct()
97 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, in enable_surface_flip_reporting()
104 struct dc_plane_state *dc_create_plane_state(struct dc *dc) in dc_create_plane_state()
106 struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state), in dc_create_plane_state()
130 const struct dc_plane_state *plane_state) in dc_plane_get_status()
175 void dc_plane_state_retain(struct dc_plane_state *plane_state) in dc_plane_state_retain()
182 struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount); in dc_plane_state_free()
187 void dc_plane_state_release(struct dc_plane_state *plane_state) in dc_plane_state_release()
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| D | dc_debug.c | 59 const struct dc_plane_state *const *plane_states, in pre_surface_trace()
66 const struct dc_plane_state *plane_state = plane_states[i]; in pre_surface_trace()
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| D | dc_resource.c | 736 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; in calculate_recout()
810 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; in calculate_scaling_ratios()
926 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; in calculate_inits_and_viewports()
1023 const struct dc_plane_state *plane_state = pipe_ctx->plane_state; in resource_build_scaling_params()
1345 struct dc_plane_state *plane_state, in dc_add_plane_to_context()
1430 struct dc_plane_state *plane_state, in dc_remove_plane_from_context()
1509 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; in dc_rem_all_planes_for_stream()
1562 struct dc_plane_state * const *plane_states, in dc_add_all_planes_for_stream()
2897 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) in dc_validate_plane()
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| D | dc.c | 1505 struct dc_plane_state *plane_state) in should_update_pipe_for_plane()
1953 const struct dc_plane_state *plane_state) in is_surface_in_context()
2322 struct dc_plane_state *surface, in copy_surface_update_to_plane()
2613 struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; in update_planes_and_stream_state()
2645 struct dc_plane_state *surface = srf_updates[i].surface; in update_planes_and_stream_state()
2903 struct dc_plane_state *plane_state = srf_updates[i].surface; in commit_planes_for_stream()
2980 struct dc_plane_state *plane_state = srf_updates[i].surface; in commit_planes_for_stream()
2999 struct dc_plane_state *plane_state = srf_updates[i].surface; in commit_planes_for_stream()
3099 struct dc_plane_state *plane_state = stream_status->plane_states[j]; in commit_minimal_transition_state()
3276 struct dc_plane_state *surface = srf_updates[i].surface; in dc_commit_updates_for_stream()
[all …]
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_color.c | 454 struct dc_plane_state *dc_plane_state) in amdgpu_dm_update_plane_color_mgmt() argument
462 switch (dc_plane_state->format) { in amdgpu_dm_update_plane_color_mgmt()
477 dc_plane_state->in_transfer_func->type = in amdgpu_dm_update_plane_color_mgmt()
505 dc_plane_state->in_transfer_func->tf = tf; in amdgpu_dm_update_plane_color_mgmt()
507 dc_plane_state->in_transfer_func->tf = in amdgpu_dm_update_plane_color_mgmt()
510 r = __set_input_tf(dc_plane_state->in_transfer_func, in amdgpu_dm_update_plane_color_mgmt()
519 dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; in amdgpu_dm_update_plane_color_mgmt()
520 dc_plane_state->in_transfer_func->tf = tf; in amdgpu_dm_update_plane_color_mgmt()
524 dc_plane_state->in_transfer_func, NULL, false)) in amdgpu_dm_update_plane_color_mgmt()
528 dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; in amdgpu_dm_update_plane_color_mgmt()
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| D | amdgpu_dm.h | 70 struct dc_plane_state;
626 struct dc_plane_state *dc_state;
729 struct dc_plane_state *dc_plane_state);
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| D | amdgpu_dm.c | 5561 struct dc_plane_state *dc_plane_state, in fill_dc_plane_attributes() argument
5576 dc_plane_state->src_rect = scaling_info.src_rect; in fill_dc_plane_attributes()
5577 dc_plane_state->dst_rect = scaling_info.dst_rect; in fill_dc_plane_attributes()
5578 dc_plane_state->clip_rect = scaling_info.clip_rect; in fill_dc_plane_attributes()
5579 dc_plane_state->scaling_quality = scaling_info.scaling_quality; in fill_dc_plane_attributes()
5585 &dc_plane_state->address, in fill_dc_plane_attributes()
5591 dc_plane_state->format = plane_info.format; in fill_dc_plane_attributes()
5592 dc_plane_state->color_space = plane_info.color_space; in fill_dc_plane_attributes()
5593 dc_plane_state->format = plane_info.format; in fill_dc_plane_attributes()
5594 dc_plane_state->plane_size = plane_info.plane_size; in fill_dc_plane_attributes()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.h | 56 const struct dc_plane_state *plane_state);
60 const struct dc_plane_state *plane_state);
68 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
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| D | dcn30_hwseq.c | 72 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) in dcn30_set_blend_lut()
146 const struct dc_plane_state *plane_state) in dcn30_set_input_transfer_func()
741 struct dc_plane_state *plane = NULL; in dcn30_apply_idle_power_optimizations()
930 bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_att… in dcn30_does_plane_fit_in_mall()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 286 struct dc_plane_state;
893 struct dc_plane_state { struct
981 struct dc_plane_state *surface;
1005 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1007 const struct dc_plane_state *plane_state);
1009 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1010 void dc_plane_state_release(struct dc_plane_state *plane_state);
1046 struct dc_plane_state *plane_states[MAX_SURFACES];
1054 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1203 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
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| D | dc_stream.h | 47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
93 struct dc_plane_state *writeback_source_plane;
370 struct dc_plane_state *plane_state,
376 struct dc_plane_state *plane_state,
387 struct dc_plane_state * const *plane_states,
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer_private.h | 83 const struct dc_plane_state *plane_state);
138 const struct dc_plane_state *plane_state);
140 const struct dc_plane_state *plane_state);
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| D | core_types.h | 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
151 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
163 struct dc_plane_state *plane_state);
347 struct dc_plane_state *plane_state;
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| D | resource.h | 136 struct dc_plane_state *const *plane_state,
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| D | hw_sequencer.h | 219 bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane,
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.h | 32 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
44 const struct dc_plane_state *plane_state);
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| D | dcn20_resource.h | 171 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);
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| D | dcn20_hwseq.c | 833 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) in dcn20_set_blend_lut()
855 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) in dcn20_set_shaper_3dlut()
885 const struct dc_plane_state *plane_state) in dcn20_set_input_transfer_func()
1407 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn20_update_dchubp_dpp()
2093 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
2122 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dcn20_update_plane_addr()
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| /drivers/gpu/drm/amd/display/dc/basics/ |
| D | dc_common.h | 40 const struct dc_plane_state *plane_state);
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| D | dc_common.c | 82 const struct dc_plane_state *plane_state) in build_prescale_params()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.h | 42 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps…
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| /drivers/gpu/drm/amd/display/include/ |
| D | logger_interface.h | 45 const struct dc_plane_state *const *plane_states,
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| /drivers/gpu/drm/amd/display/modules/inc/ |
| D | mod_freesync.h | 162 const struct dc_plane_state *plane,
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.h | 72 const struct dc_plane_state *plane_state);
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_hw_sequencer.c | 274 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in dce60_program_front_end_for_pipe()
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