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Searched refs:dcc_rate (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_structs.h240 unsigned int dcc_rate; member
Ddisplay_mode_lib.c160 dml_print("DML PARAMS: dcc_rate = %d\n", pipe_src->dcc_rate); in dml_log_pipe_params()
Ddisplay_mode_vba.c460 mode_lib->vba.DCCRate[mode_lib->vba.NumberOfActivePlanes] = src->dcc_rate; in fetch_pipe_params()
462 mode_lib->vba.DCCRateLuma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_rate; in fetch_pipe_params()
/drivers/gpu/drm/amd/display/dc/inc/
Ddcn_calcs.h183 float dcc_rate[number_of_planes_minus_one + 1]; member
/drivers/clk/ti/
Ddpll.c538 .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ in of_ti_omap5_mpu_dpll_setup()
Ddpll3xxx.c410 if (dd->last_rounded_rate >= dd->dcc_rate) in omap3_noncore_dpll_program()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c336 input->src.dcc_rate = 1; in pipe_ctx_to_e2e_pipe_params()
1045 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/ in dcn_validate_bandwidth()
Ddcn_calc_auto.c1370 …d + v->read_bandwidth_plane_luma[k] / v->dcc_rate[k] / 1000.0 + v->read_bandwidth_plane_chroma[k] … in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c1613 pipes[pipe_cnt].pipe.src.dcc_rate = 3; in dcn31_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c2049 pipes[pipe_cnt].pipe.src.dcc_rate = 1; in dcn20_populate_dml_pipes_from_context()