| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 172 .dispclk_mhz = 600.0,
183 .dispclk_mhz = 654.55,
194 .dispclk_mhz = 757.89,
205 .dispclk_mhz = 847.06,
216 .dispclk_mhz = 900.00,
227 .dispclk_mhz = 1028.57,
238 .dispclk_mhz = 1107.69,
249 .dispclk_mhz = 1395.0,
261 .dispclk_mhz = 1395.0,
1118 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context… in dcn21_calculate_wm()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 178 .dispclk_mhz = 1015.0,
189 .dispclk_mhz = 1015.0,
200 .dispclk_mhz = 1015.0,
212 .dispclk_mhz = 1015.0,
224 .dispclk_mhz = 1015.0,
1605 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn301_update_bw_bounding_box()
1705 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg()
1709 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg()
1712 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_calculate_wm_and_dlg()
1713 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 173 .dispclk_mhz = 1200.0,
182 .dispclk_mhz = 1200.0,
191 .dispclk_mhz = 1200.0,
200 .dispclk_mhz = 1200.0,
209 .dispclk_mhz = 1200.0,
1776 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1780 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1783 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
1784 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
1882 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 237 .dispclk_mhz = 513.0,
248 .dispclk_mhz = 642.0,
259 .dispclk_mhz = 734.0,
270 .dispclk_mhz = 1100.0,
281 .dispclk_mhz = 1284.0,
293 .dispclk_mhz = 1284.0,
348 .dispclk_mhz = 513.0,
359 .dispclk_mhz = 642.0,
370 .dispclk_mhz = 734.0,
381 .dispclk_mhz = 1100.0,
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_socbb.h | 33 uint32_t dispclk_mhz; member
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_structs.h | 65 double dispclk_mhz; member
376 double dispclk_mhz; member
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| D | display_mode_vba.c | 288 mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz; in fetch_socbb_params()
888 if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0) in ModeSupportAndSystemConfiguration()
889 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz; in ModeSupportAndSystemConfiguration()
891 mode_lib->vba.DISPCLK = soc->clock_limits[mode_lib->vba.VoltageLevel].dispclk_mhz; in ModeSupportAndSystemConfiguration()
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| D | display_mode_lib.c | 255 dml_print("DML PARAMS: dispclk_mhz = %3.2f\n", clks_cfg->dispclk_mhz); in dml_log_pipe_params()
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| D | dml1_display_rq_dlg_calc.c | 1020 double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz; in dml1_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 175 .dispclk_mhz = 562.0,
2251 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg_fp()
2255 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2258 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn30_calculate_wm_and_dlg_fp()
2259 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn30_calculate_wm_and_dlg_fp()
2410 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn30_update_bw_bounding_box()
2411 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn30_update_bw_bounding_box()
2421 max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; in dcn30_update_bw_bounding_box()
2503 dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn30_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 91 unsigned int dispclk_mhz; member
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 157 .dispclk_mhz = 562.0,
1312 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_update_bw_bounding_box()
1313 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_update_bw_bounding_box()
1322 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; in dcn302_update_bw_bounding_box()
1402 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn302_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 139 .dispclk_mhz = 1217.0,
1242 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_update_bw_bounding_box()
1243 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_update_bw_bounding_box()
1252 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; in dcn303_update_bw_bounding_box()
1330 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn303_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 201 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 599 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in dcn31_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 814 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.c | 814 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml20_rq_dlg_get_dlg_params()
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| D | display_mode_vba_20.c | 1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| D | display_mode_vba_20v2.c | 1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 860 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml_rq_dlg_get_dlg_params()
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| D | display_mode_vba_21.c | 1642 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 1014 double dispclk_freq_in_mhz = clks->dispclk_mhz; in dml_rq_dlg_get_dlg_params()
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| D | display_mode_vba_30.c | 2059 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 492 input.clks_cfg.dispclk_mhz = v->dispclk; in dcn_bw_calc_rq_dlg_ttu()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_mode_vba_31.c | 2183 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
|