| /drivers/clk/renesas/ |
| D | rcar-cpg-lib.c | 89 const struct sd_div_table *div_table; member
135 clock->div_table[clock->cur_div_idx].val & in cpg_sd_clock_enable()
161 clock->div_table[clock->cur_div_idx].div); in cpg_sd_clock_recalc_rate()
174 clock->div_table[i].div); in cpg_sd_clock_determine_rate()
201 clock->div_table[i].div)) in cpg_sd_clock_set_rate()
210 clock->div_table[i].val & in cpg_sd_clock_set_rate()
246 clock->div_table = cpg_sd_div_table; in cpg_sd_clk_register()
250 clock->div_table++; in cpg_sd_clk_register()
255 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK); in cpg_sd_clk_register()
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| D | r9a06g032-clocks.c | 44 u16 div_table[4]; member
83 .div_table = { __VA_ARGS__ } }
698 i < ARRAY_SIZE(desc->div_table) && desc->div_table[i]; i++) { in r9a06g032_register_div()
699 div->table[div->table_size++] = desc->div_table[i]; in r9a06g032_register_div()
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| /drivers/clk/ti/ |
| D | divider.c | 339 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, in ti_clk_parse_divider_data() argument
347 if (!div_table) { in ti_clk_parse_divider_data()
357 if (div_table[i] == -1) in ti_clk_parse_divider_data()
359 if (div_table[i]) in ti_clk_parse_divider_data()
373 if (div_table[i] > 0) { in ti_clk_parse_divider_data()
374 tmp[valid_div].div = div_table[i]; in ti_clk_parse_divider_data()
377 if (div_table[i] > max_div) in ti_clk_parse_divider_data()
378 max_div = div_table[i]; in ti_clk_parse_divider_data()
379 if (!min_div || div_table[i] < min_div) in ti_clk_parse_divider_data()
380 min_div = div_table[i]; in ti_clk_parse_divider_data()
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| D | clock.h | 225 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
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| /drivers/clk/mediatek/ |
| D | clk-pll.c | 165 const struct mtk_pll_div_table *div_table = pll->data->div_table; in mtk_pll_calc_values() local
173 if (div_table) { in mtk_pll_calc_values()
174 if (freq > div_table[0].freq) in mtk_pll_calc_values()
175 freq = div_table[0].freq; in mtk_pll_calc_values()
177 for (val = 0; div_table[val + 1].freq != 0; val++) { in mtk_pll_calc_values()
178 if (freq > div_table[val + 1].freq) in mtk_pll_calc_values()
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| D | clk-mtk.h | 235 const struct mtk_pll_div_table *div_table; member
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| D | clk-mt7629.c | 41 .div_table = _div_table, \
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| D | clk-mt6797.c | 632 .div_table = _div_table, \
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| D | clk-mt7622.c | 41 .div_table = _div_table, \
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| D | clk-mt8516.c | 753 .div_table = _div_table, \
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| D | clk-mt6779.c | 1169 .div_table = _div_table, \
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| /drivers/clk/ingenic/ |
| D | cgu.c | 399 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
400 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
420 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
421 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
422 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
423 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
449 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
452 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
517 if (clk_info->div.div_table) in ingenic_clk_set_rate()
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| D | cgu.h | 102 const u8 *div_table; member
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| /drivers/clk/mmp/ |
| D | clk-mix.c | 37 if (mix->div_table) { in _get_maxdiv()
38 for (clkt = mix->div_table; clkt->div; clkt++) in _get_maxdiv()
54 if (mix->div_table) { in _get_div()
55 for (clkt = mix->div_table; clkt->div; clkt++) in _get_div()
91 if (mix->div_table) { in _get_div_val()
92 for (clkt = mix->div_table; clkt->div; clkt++) in _get_div_val()
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| D | clk.h | 81 struct clk_div_table *div_table; member
91 struct clk_div_table *div_table; member
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| /drivers/clk/ |
| D | clk-aspeed.c | 171 .div_table = ast2500_div_table,
178 .div_table = ast2400_div_table,
451 soc_data->div_table, in aspeed_clk_probe()
493 soc_data->div_table, in aspeed_clk_probe()
502 soc_data->div_table, in aspeed_clk_probe()
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| D | clk-aspeed.h | 78 const struct clk_div_table *div_table; member
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| D | clk-stm32f4.c | 533 const struct clk_div_table *div_table; member
570 const struct clk_div_table *div_table; member
837 div_data[i].div_table, in stm32f4_rcc_register_pll()
1772 post_div->div_table, in stm32f4_rcc_init()
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| /drivers/clk/rockchip/ |
| D | clk.c | 44 struct clk_div_table *div_table, int gate_offset, in rockchip_clk_register_branch() argument
99 div->table = div_table; in rockchip_clk_register_branch()
461 if (list->div_table) in rockchip_clk_register_branches()
467 list->div_flags, list->div_table, in rockchip_clk_register_branches()
510 list->div_flags, list->div_table, in rockchip_clk_register_branches()
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| D | clk.h | 455 struct clk_div_table *div_table; member
536 .div_table = dt, \
595 .div_table = dt, \
725 .div_table = dt, \
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| /drivers/clk/x86/ |
| D | clk-cgu.h | 188 const struct clk_div_table *div_table; member
238 .div_table = _dtable, \
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| D | clk-cgu.c | 224 div->table = list->div_table; in lgm_clk_register_divider()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 266 const u8 *div_table; in g33_get_cdclk() local
281 div_table = div_3200; in g33_get_cdclk()
284 div_table = div_4000; in g33_get_cdclk()
287 div_table = div_4800; in g33_get_cdclk()
290 div_table = div_5333; in g33_get_cdclk()
297 div_table[cdclk_sel]); in g33_get_cdclk()
348 const u8 *div_table; in i965gm_get_cdclk() local
363 div_table = div_3200; in i965gm_get_cdclk()
366 div_table = div_4000; in i965gm_get_cdclk()
369 div_table = div_5333; in i965gm_get_cdclk()
[all …]
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-meson8b.c | 151 static const struct clk_div_table div_table[] = { in meson8b_init_rgmii_tx_clk() local
181 clk_configs->m250_div.table = div_table; in meson8b_init_rgmii_tx_clk()
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| /drivers/clk/qcom/ |
| D | gcc-ipq4019.c | 76 const struct clk_div_table *div_table; member
1394 for (clkt = pll->div_table; clkt->div; clkt++) { in clk_regmap_clk_div_recalc_rate()
1507 .div_table = fepllwcss_clk_div_table,
1525 .div_table = fepllwcss_clk_div_table,
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