| /drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 123 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
198 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
208 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
[all …]
|
| D | rv730_dpm.c | 42 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
61 if (dividers.enable_post_div) in rv730_populate_sclk_value()
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
72 if (dividers.enable_post_div) in rv730_populate_sclk_value()
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
[all …]
|
| D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs, in rv6xx_program_engine_spread_spectrum()
[all …]
|
| D | rv770_dpm.c | 322 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
404 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
412 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
423 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
440 if (dividers.vco_mode) in rv770_populate_mclk_value()
[all …]
|
| D | cypress_dpm.c | 493 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
508 dividers.post_div = 1; in cypress_populate_mclk_value()
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
524 if (dividers.vco_mode) in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
[all …]
|
| D | rs780_dpm.c | 78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1033 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1044 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1048 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1051 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
[all …]
|
| D | radeon_atombios.c | 2835 struct atom_clock_dividers *dividers) in radeon_atom_get_clock_dividers() argument
2842 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in radeon_atom_get_clock_dividers()
2855 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2856 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2857 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2869 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2870 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2871 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2873 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()
2875 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()
[all …]
|
| D | ni_dpm.c | 2004 struct atom_clock_dividers dividers; in ni_calculate_sclk_params() local
2018 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
2031 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in ni_calculate_sclk_params()
2042 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2177 struct atom_clock_dividers dividers; in ni_populate_mclk_value() local
2184 memory_clock, strobe_mode, ÷rs); in ni_populate_mclk_value()
2192 dividers.post_div = 1; in ni_populate_mclk_value()
[all …]
|
| D | kv_dpm.c | 380 struct atom_clock_dividers dividers; in kv_set_divider_value() local
384 sclk, false, ÷rs); in kv_set_divider_value()
388 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
665 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
688 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
691 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
694 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
697 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
738 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
756 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
[all …]
|
| /drivers/gpu/drm/amd/display/modules/color/ |
| D | color_gamma.c | 284 struct dividers { struct
1173 struct dividers dividers) in scale_gamma() argument
1209 dividers.divider1); in scale_gamma()
1211 dividers.divider1); in scale_gamma()
1213 dividers.divider1); in scale_gamma()
1218 dividers.divider2); in scale_gamma()
1220 dividers.divider2); in scale_gamma()
1222 dividers.divider2); in scale_gamma()
1227 dividers.divider3); in scale_gamma()
1229 dividers.divider3); in scale_gamma()
[all …]
|
| /drivers/clk/baikal-t1/ |
| D | Kconfig | 12 configurable and fixed clock dividers. Enable this option to be able
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
36 Enable this to support the CCU dividers used to distribute clocks
38 SoC. CCU dividers can be either configurable or with fixed divider,
39 either gateable or ungateable. Some of the CCU dividers can be as well
|
| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | ppatomctrl.c | 389 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong() argument
402 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
403 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
412 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi() argument
426 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
428 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
431 dividers->ul_fb_div.ul_fb_div_frac = in atomctrl_get_engine_pll_dividers_vi()
433 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
436 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
438 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
[all …]
|
| D | ppatomctrl.h | 308 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
309 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
318 pp_atomctrl_clock_dividers_kong *dividers);
323 …dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
|
| D | ppatomfwctrl.c | 248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
|
| D | smu8_hwmgr.c | 441 pp_atomctrl_clock_dividers_kong dividers; in smu8_upload_pptable_to_smu() local
486 ÷rs); in smu8_upload_pptable_to_smu()
489 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
503 ÷rs); in smu8_upload_pptable_to_smu()
506 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
517 ÷rs); in smu8_upload_pptable_to_smu()
520 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
529 ÷rs); in smu8_upload_pptable_to_smu()
532 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
543 ÷rs); in smu8_upload_pptable_to_smu()
[all …]
|
| D | vega10_hwmgr.c | 1496 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_lclk_level() local
1501 lclock, ÷rs), in vega10_populate_single_lclk_level()
1505 *curr_lclk_did = dividers.ulDid; in vega10_populate_single_lclk_level()
1614 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_gfx_level() local
1643 gfx_clock, ÷rs), in vega10_populate_single_gfx_level()
1649 cpu_to_le32(dividers.ulPll_fb_mult); in vega10_populate_single_gfx_level()
1651 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; in vega10_populate_single_gfx_level()
1653 cpu_to_le32(dividers.ulPll_ss_fbsmult); in vega10_populate_single_gfx_level()
1655 cpu_to_le16(dividers.usPll_ss_slew_frac); in vega10_populate_single_gfx_level()
1656 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); in vega10_populate_single_gfx_level()
[all …]
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 1000 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers() argument
1007 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1024 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1026 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1028 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1029 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1030 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1031 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1043 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
[all …]
|
| D | amdgpu_atombios.h | 161 struct atom_clock_dividers *dividers);
202 struct atom_clock_dividers *dividers);
|
| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | polaris10_smumgr.c | 895 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in polaris10_calculate_sclk_params()
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
909 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
913 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
914 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
915 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in polaris10_calculate_sclk_params()
[all …]
|
| D | vegam_smumgr.c | 725 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
734 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
737 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
738 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
739 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
741 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
743 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
744 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
745 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in vegam_calculate_sclk_params()
[all …]
|
| D | fiji_smumgr.c | 859 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
871 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in fiji_calculate_sclk_params()
879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
886 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
888 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
902 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
931 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in fiji_calculate_sclk_params()
1303 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acpi_level() local
1334 table->ACPILevel.SclkFrequency, ÷rs); in fiji_populate_smc_acpi_level()
[all …]
|
| D | ci_smumgr.c | 300 struct pp_atomctrl_clock_dividers_vi dividers; in ci_calculate_sclk_params() local
312 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in ci_calculate_sclk_params()
320 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()
323 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
327 SPLL_REF_DIV, dividers.uc_pll_ref_div); in ci_calculate_sclk_params()
329 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
342 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()
365 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in ci_calculate_sclk_params()
1381 struct pp_atomctrl_clock_dividers_vi dividers; in ci_populate_smc_acpi_level() local
1404 table->ACPILevel.SclkFrequency, ÷rs); in ci_populate_smc_acpi_level()
[all …]
|
| D | tonga_smumgr.c | 542 pp_atomctrl_clock_dividers_vi dividers; in tonga_calculate_sclk_params() local
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
562 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in tonga_calculate_sclk_params()
569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
611 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in tonga_calculate_sclk_params()
1180 struct pp_atomctrl_clock_dividers_vi dividers; in tonga_populate_smc_acpi_level() local
1199 table->ACPILevel.SclkFrequency, ÷rs); in tonga_populate_smc_acpi_level()
[all …]
|
| /drivers/clk/mstar/ |
| D | Kconfig | 8 Support for the MPLL PLL and dividers block present on
|
| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | kv_dpm.c | 665 struct atom_clock_dividers dividers; in kv_set_divider_value() local
669 sclk, false, ÷rs); in kv_set_divider_value()
673 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
906 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
929 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
932 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
935 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
938 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
979 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
997 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
[all …]
|