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Searched refs:dml_ceil (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_mode_vba_21.c755 *VUpdateOffsetPix = dml_ceil(myPipe->HTotal / 4.0, 1); in CalculatePrefetchSchedule()
808 …*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockWidth256BytesY) + myPipe->BlockWidth… in CalculatePrefetchSchedule()
809 …*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockWidth256BytesC) + myPipe->Bloc… in CalculatePrefetchSchedule()
811 …*swath_width_luma_ub = dml_ceil(SwathWidthY - 1, myPipe->BlockHeight256BytesY) + myPipe->BlockHeig… in CalculatePrefetchSchedule()
812 …*swath_width_chroma_ub = dml_ceil(SwathWidthY / 2 - 1, myPipe->BlockHeight256BytesC) + myPipe->Blo… in CalculatePrefetchSchedule()
815 …LinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) + PrefetchSourceLinesC * *swath_widt… in CalculatePrefetchSchedule()
832 Tvm_oto_lines = dml_ceil(4 * Tvm_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
833 Tr0_oto_lines = dml_ceil(4 * Tr0_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
834 Tsw_oto_lines = dml_ceil(4 * Tsw_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
867 + PrefetchSourceLinesY * *swath_width_luma_ub * dml_ceil(BytePerPixelDETY, 1) in CalculatePrefetchSchedule()
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Ddisplay_rq_dlg_calc_21.c451 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
687 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( in get_meta_and_pte_attr()
1763 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) in calculate_ttu_cursor()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_mode_vba_20.c546 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); in CalculatePrefetchSchedule()
601 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1) in CalculatePrefetchSchedule()
602 + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2)) in CalculatePrefetchSchedule()
657 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1) in CalculatePrefetchSchedule()
659 * dml_ceil(BytePerPixelDETC, 2)) in CalculatePrefetchSchedule()
765 * dml_ceil( in CalculatePrefetchSchedule()
770 * dml_ceil( in CalculatePrefetchSchedule()
809 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1); in RoundToDFSGranularityDown()
832 *MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0; in CalculatePrefetchSourceLines()
847 *MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1); in CalculatePrefetchSourceLines()
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Ddisplay_mode_vba_20v2.c503 …DataFabricLineDeliveryTimeLuma = SwathWidthSingleDPPY * SwathHeightY * dml_ceil(BytePerPixelDETY, … in CalculateDelayAfterScaler()
507 …DataFabricLineDeliveryTimeChroma = SwathWidthSingleDPPY / 2 * SwathHeightC * dml_ceil(BytePerPixel… in CalculateDelayAfterScaler()
609 *VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1); in CalculatePrefetchSchedule()
661 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1) in CalculatePrefetchSchedule()
662 + PrefetchSourceLinesC * SwathWidthY / 2 * dml_ceil(BytePerPixelDETC, 2)) in CalculatePrefetchSchedule()
717 + PrefetchSourceLinesY * SwathWidthY * dml_ceil(BytePerPixelDETY, 1) in CalculatePrefetchSchedule()
719 * dml_ceil(BytePerPixelDETC, 2)) in CalculatePrefetchSchedule()
825 * dml_ceil( in CalculatePrefetchSchedule()
830 * dml_ceil( in CalculatePrefetchSchedule()
869 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1); in RoundToDFSGranularityDown()
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Ddisplay_rq_dlg_calc_20v2.c459 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
680 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, in get_meta_and_pte_attr()
1642 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) in calculate_ttu_cursor()
Ddisplay_rq_dlg_calc_20.c459 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
680 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, in get_meta_and_pte_attr()
1641 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) in calculate_ttu_cursor()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c1059 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime; in CalculatePrefetchSchedule()
1060 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime; in CalculatePrefetchSchedule()
1094 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1095 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0; in CalculatePrefetchSchedule()
1257 …*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.… in CalculatePrefetchSchedule()
1259 …*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0)… in CalculatePrefetchSchedule()
1374 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1); in RoundToDFSGranularityDown()
1516 full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256); in CalculateDCCConfiguration()
1517 full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256); in CalculateDCCConfiguration()
1518 full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256); in CalculateDCCConfiguration()
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Ddisplay_rq_dlg_calc_30.c496 + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
742 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, in get_meta_and_pte_attr()
931 cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) in calculate_ttu_cursor()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c1081 Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
1082 Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
1117 Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
1156 Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
1157 Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
1332 …*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.…
1334 …*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0)…
1521 return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
1642 full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256);
1643 full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256);
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Ddisplay_rq_dlg_calc_31.c512 log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_meta_and_pte_attr()
733 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1); in get_meta_and_pte_attr()
908 …cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_wid… in calculate_ttu_cursor()
/drivers/gpu/drm/amd/display/dc/dml/
Ddml_inline_defs.h67 static inline double dml_ceil(double a, double granularity) in dml_ceil() function
80 double ceil = dml_ceil(a, 1); in dml_round()
Ddisplay_mode_vba.c914 dml_ceil(WritebackLumaHTaps / 4.0, 1) / WritebackHRatio, in CalculateWriteBackDISPCLK()
915 …dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWi… in CalculateWriteBackDISPCLK()
916 …+ dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio… in CalculateWriteBackDISPCLK()
917 * (dml_ceil(WritebackLumaVTaps / 4.0, 1) + 4.0) / (double) HTotal, in CalculateWriteBackDISPCLK()
918 dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal)); in CalculateWriteBackDISPCLK()
921 dml_ceil(WritebackChromaHTaps / 2.0, 1) / (2 * WritebackHRatio), in CalculateWriteBackDISPCLK()
922 …dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestina… in CalculateWriteBackDISPCLK()
923 + dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal in CalculateWriteBackDISPCLK()
924 … + dml_ceil(1 / (2 * WritebackVRatio), 1) * (dml_ceil(WritebackChromaVTaps / 4.0, 1) + 4) / HTotal, in CalculateWriteBackDISPCLK()
925 dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal))); in CalculateWriteBackDISPCLK()
Ddml1_display_rq_dlg_calc.c185 …*max_num_sw = (unsigned int) (dml_ceil((prefill - 1.0) / (double) swath_height, 1) + 1.0); /* pref… in get_swath_need()
447 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in dml1_rq_dlg_get_row_heights()
687 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); in get_surf_rq_param()
923 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( in get_surf_rq_param()
1855 cur0_width_ub = dml_ceil((double) cur0_src_width / (double) cur0_req_width, 1) in dml1_rq_dlg_get_dlg_params()