| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 173 .dppclk_mhz = 400.00,
184 .dppclk_mhz = 626.09,
195 .dppclk_mhz = 685.71,
206 .dppclk_mhz = 757.89,
217 .dppclk_mhz = 847.06,
228 .dppclk_mhz = 960.00,
239 .dppclk_mhz = 1028.57,
250 .dppclk_mhz = 1285.00,
262 .dppclk_mhz = 1285.0,
1121 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn21_calculate_wm()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 177 .dppclk_mhz = 1015.0,
188 .dppclk_mhz = 1015.0,
199 .dppclk_mhz = 1015.0,
211 .dppclk_mhz = 1015.0,
223 .dppclk_mhz = 1015.0,
1606 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_update_bw_bounding_box()
1706 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_calculate_wm_and_dlg()
1710 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_calculate_wm_and_dlg()
1714 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_calculate_wm_and_dlg()
1715 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 238 .dppclk_mhz = 513.0,
249 .dppclk_mhz = 642.0,
260 .dppclk_mhz = 734.0,
271 .dppclk_mhz = 1100.0,
282 .dppclk_mhz = 1284.0,
294 .dppclk_mhz = 1284.0,
349 .dppclk_mhz = 513.0,
360 .dppclk_mhz = 642.0,
371 .dppclk_mhz = 734.0,
382 .dppclk_mhz = 1100.0,
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 174 .dppclk_mhz = 1200.0,
183 .dppclk_mhz = 1200.0,
192 .dppclk_mhz = 1200.0,
201 .dppclk_mhz = 1200.0,
210 .dppclk_mhz = 1200.0,
1777 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
1781 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1785 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
1786 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
1884 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_socbb.h | 35 uint32_t dppclk_mhz; member
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_structs.h | 68 double dppclk_mhz; member
374 double dppclk_mhz; member
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| D | display_mode_lib.c | 253 dml_print("DML PARAMS: dppclk_mhz = %3.2f\n", clks_cfg->dppclk_mhz); in dml_log_pipe_params()
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| D | display_mode_vba.c | 67 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
284 mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz; in fetch_socbb_params()
555 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz; in fetch_pipe_params()
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| D | dml1_display_rq_dlg_calc.c | 1019 double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 176 .dppclk_mhz = 300.0,
2252 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_calculate_wm_and_dlg_fp()
2256 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2260 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn30_calculate_wm_and_dlg_fp()
2261 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn30_calculate_wm_and_dlg_fp()
2412 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn30_update_bw_bounding_box()
2413 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn30_update_bw_bounding_box()
2423 max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_update_bw_bounding_box()
2504 dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn30_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 92 unsigned int dppclk_mhz; member
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 158 .dppclk_mhz = 300.0,
1314 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_update_bw_bounding_box()
1315 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_update_bw_bounding_box()
1324 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_update_bw_bounding_box()
1403 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn302_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 140 .dppclk_mhz = 1217.0,
1244 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_update_bw_bounding_box()
1245 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_update_bw_bounding_box()
1254 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz; in dcn303_update_bw_bounding_box()
1331 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn303_update_bw_bounding_box()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 206 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 600 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk; in dcn31_clk_mgr_helper_populate_bw_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 813 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml20v2_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.c | 813 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml20_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 859 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 971 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 1013 double dppclk_freq_in_mhz = clks->dppclk_mhz; in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 493 input.clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
|