Searched refs:dramclk_khz (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 281 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn2_update_clocks()
282 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn2_update_clocks()
284 …p_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); in dcn2_update_clocks()
361 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) { in dcn2_update_clocks_fpga()
362 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn2_update_clocks_fpga()
476 else if (a->dramclk_khz != b->dramclk_khz) in dcn2_are_clock_states_equal()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 312 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) { in dcn3_update_clocks()
313 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn3_update_clocks()
320 …n30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); in dcn3_update_clocks()
402 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)); in dcn3_set_hard_min_memclk()
463 else if (a->dramclk_khz != b->dramclk_khz) in dcn3_are_clock_states_equal()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_trace.h | 500 __field(int, dramclk_khz)
518 __entry->dramclk_khz = clk->dramclk_khz;
543 __entry->dramclk_khz,
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 386 int dramclk_khz; member
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 3611 info->memoryClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dramclk_khz; in get_clock_requirements_for_state()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 3098 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
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