| /drivers/gpu/drm/msm/dp/ |
| D | dp_panel.c | 319 dp_catalog_panel_tpg_enable(catalog, &panel->dp_panel.dp_mode.drm_mode); in dp_panel_tpg_config()
338 struct drm_display_mode *drm_mode; in dp_panel_timing_cfg() local
342 drm_mode = &panel->dp_panel.dp_mode.drm_mode; in dp_panel_timing_cfg()
345 drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end, in dp_panel_timing_cfg()
346 drm_mode->hsync_start - drm_mode->hdisplay, in dp_panel_timing_cfg()
347 drm_mode->hsync_end - drm_mode->hsync_start); in dp_panel_timing_cfg()
350 drm_mode->vdisplay, drm_mode->vtotal - drm_mode->vsync_end, in dp_panel_timing_cfg()
351 drm_mode->vsync_start - drm_mode->vdisplay, in dp_panel_timing_cfg()
352 drm_mode->vsync_end - drm_mode->vsync_start); in dp_panel_timing_cfg()
354 total_hor = drm_mode->htotal; in dp_panel_timing_cfg()
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| D | dp_debug.c | 55 struct drm_display_mode *drm_mode; in dp_debug_read_info() local
67 drm_mode = &debug->panel->dp_mode.drm_mode; in dp_debug_read_info()
99 drm_mode->hdisplay, in dp_debug_read_info()
100 drm_mode->vdisplay); in dp_debug_read_info()
106 drm_mode->htotal - drm_mode->hsync_end, in dp_debug_read_info()
107 drm_mode->vtotal - drm_mode->vsync_end); in dp_debug_read_info()
113 drm_mode->hsync_start - drm_mode->hdisplay, in dp_debug_read_info()
114 drm_mode->vsync_start - drm_mode->vdisplay); in dp_debug_read_info()
120 drm_mode->hsync_end - drm_mode->hsync_start, in dp_debug_read_info()
121 drm_mode->vsync_end - drm_mode->vsync_start); in dp_debug_read_info()
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| D | dp_drm.c | 50 struct drm_display_mode *m, drm_mode; in dp_connector_get_modes() local
75 if (dp_mode->drm_mode.clock) { /* valid DP mode */ in dp_connector_get_modes()
76 memset(&drm_mode, 0x0, sizeof(drm_mode)); in dp_connector_get_modes()
77 drm_mode_copy(&drm_mode, &dp_mode->drm_mode); in dp_connector_get_modes()
78 m = drm_mode_duplicate(connector->dev, &drm_mode); in dp_connector_get_modes()
81 drm_mode.hdisplay, in dp_connector_get_modes()
82 drm_mode.vdisplay); in dp_connector_get_modes()
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| D | dp_catalog.c | 783 struct drm_display_mode *drm_mode) in dp_catalog_panel_tpg_enable() argument
795 hsync_period = drm_mode->htotal; in dp_catalog_panel_tpg_enable()
796 vsync_period = drm_mode->vtotal; in dp_catalog_panel_tpg_enable()
798 display_v_start = ((drm_mode->vtotal - drm_mode->vsync_start) * in dp_catalog_panel_tpg_enable()
800 display_v_end = ((vsync_period - (drm_mode->vsync_start - in dp_catalog_panel_tpg_enable()
801 drm_mode->vdisplay)) in dp_catalog_panel_tpg_enable()
804 display_v_start += drm_mode->htotal - drm_mode->hsync_start; in dp_catalog_panel_tpg_enable()
805 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); in dp_catalog_panel_tpg_enable()
807 hsync_start_x = drm_mode->htotal - drm_mode->hsync_start; in dp_catalog_panel_tpg_enable()
808 hsync_end_x = hsync_period - (drm_mode->hsync_start - in dp_catalog_panel_tpg_enable()
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| D | dp_ctrl.c | 939 struct drm_display_mode *drm_mode; in dp_ctrl_calc_tu_parameters() local
941 drm_mode = &ctrl->panel->dp_mode.drm_mode; in dp_ctrl_calc_tu_parameters()
944 in.pclk_khz = drm_mode->clock; in dp_ctrl_calc_tu_parameters()
945 in.hactive = drm_mode->hdisplay; in dp_ctrl_calc_tu_parameters()
946 in.hporch = drm_mode->htotal - drm_mode->hdisplay; in dp_ctrl_calc_tu_parameters()
1481 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; in dp_ctrl_link_maintenance()
1666 if (!ctrl->panel->dp_mode.drm_mode.clock) in dp_ctrl_on_link()
1672 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; in dp_ctrl_on_link()
1781 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; in dp_ctrl_on_stream_phy_test_report()
1805 ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; in dp_ctrl_on_stream()
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| D | dp_display.c | 844 drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode); in dp_display_set_mode()
1000 if (dp_mode->drm_mode.clock) in dp_display_get_modes()
1001 dp->max_pclk_khz = dp_mode->drm_mode.clock; in dp_display_get_modes()
1519 if (!dp_display->dp_mode.drm_mode.clock) { in msm_dp_display_enable()
1627 drm_mode_copy(&dp_display->dp_mode.drm_mode, adjusted_mode); in msm_dp_display_mode_set()
1630 !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); in msm_dp_display_mode_set()
1633 !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); in msm_dp_display_mode_set()
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| D | dp_panel.h | 23 struct drm_display_mode drm_mode; member
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| D | dp_catalog.h | 121 struct drm_display_mode *drm_mode);
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 155 struct drm_display_mode *drm_mode; in drm_cvt_mode() local
167 drm_mode = drm_mode_create(dev); in drm_cvt_mode()
168 if (!drm_mode) in drm_cvt_mode()
191 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; in drm_cvt_mode()
204 drm_mode->vdisplay = vdisplay + 2 * vmargin; in drm_cvt_mode()
253 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + in drm_cvt_mode()
273 hblank = drm_mode->hdisplay * hblank_percentage / in drm_cvt_mode()
277 drm_mode->htotal = drm_mode->hdisplay + hblank; in drm_cvt_mode()
278 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; in drm_cvt_mode()
279 drm_mode->hsync_start = drm_mode->hsync_end - in drm_cvt_mode()
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| /drivers/gpu/drm/i2c/ |
| D | ch7006_mode.c | 174 const struct drm_display_mode *drm_mode) in ch7006_lookup_mode() argument
184 if (mode->mode.hdisplay != drm_mode->hdisplay || in ch7006_lookup_mode()
185 mode->mode.vdisplay != drm_mode->vdisplay || in ch7006_lookup_mode()
186 mode->mode.vtotal != drm_mode->vtotal || in ch7006_lookup_mode()
187 mode->mode.htotal != drm_mode->htotal || in ch7006_lookup_mode()
188 mode->mode.clock != drm_mode->clock) in ch7006_lookup_mode()
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| D | ch7006_drv.c | 114 struct drm_display_mode *drm_mode, in ch7006_encoder_mode_set() argument
141 start_active = (drm_mode->htotal & ~0x7) - (drm_mode->hsync_start & ~0x7); in ch7006_encoder_mode_set()
150 if (drm_mode->flags & DRM_MODE_FLAG_PVSYNC) in ch7006_encoder_mode_set()
152 if (drm_mode->flags & DRM_MODE_FLAG_PHSYNC) in ch7006_encoder_mode_set()
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| D | ch7006_priv.h | 114 const struct drm_display_mode *drm_mode);
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 5986 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, in decide_crtc_timing_for_drm_display_mode() argument
5991 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); in decide_crtc_timing_for_drm_display_mode()
5992 } else if (native_mode->clock == drm_mode->clock && in decide_crtc_timing_for_drm_display_mode()
5993 native_mode->htotal == drm_mode->htotal && in decide_crtc_timing_for_drm_display_mode()
5994 native_mode->vtotal == drm_mode->vtotal) { in decide_crtc_timing_for_drm_display_mode()
5995 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); in decide_crtc_timing_for_drm_display_mode()
6255 const struct drm_display_mode *drm_mode, in create_stream_for_sink() argument
6265 struct drm_display_mode mode = *drm_mode; in create_stream_for_sink()
6908 const struct drm_display_mode *drm_mode, in create_validate_stream_for_sink() argument
6920 stream = create_stream_for_sink(aconnector, drm_mode, in create_validate_stream_for_sink()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | tvnv17.c | 458 struct drm_display_mode *drm_mode, in nv17_tv_mode_set() argument
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