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Searched refs:dsc (Results 1 – 25 of 48) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c30 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
35 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
41 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
42 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *ds…
43 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
45 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc…
46 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
47 static void dsc2_disable(struct display_stream_compressor *dsc);
70 dsc->ctx->logger
81 void dsc2_construct(struct dcn20_dsc *dsc, in dsc2_construct() argument
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Ddcn20_resource.h97 void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
133 struct display_stream_compressor **dsc);
147 struct display_stream_compressor **dsc,
Ddcn20_resource.c1442 struct dcn20_dsc *dsc = in dcn20_dsc_create() local
1445 if (!dsc) { in dcn20_dsc_create()
1450 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); in dcn20_dsc_create()
1451 return &dsc->base; in dcn20_dsc_create()
1454 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) in dcn20_dsc_destroy() argument
1456 kfree(container_of(*dsc, struct dcn20_dsc, base)); in dcn20_dsc_destroy()
1457 *dsc = NULL; in dcn20_dsc_destroy()
1671 struct display_stream_compressor **dsc, in dcn20_acquire_dsc() argument
1676 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1678 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ in dcn20_acquire_dsc()
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/drivers/gpu/drm/i915/display/
Dintel_vdsc.c451 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
452 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
460 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
579 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure()
584 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; in intel_dsc_pps_configure()
611 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
618 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
635 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
642 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
660 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
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Dintel_bios.c66 struct dsc_compression_parameters_entry *dsc; member
1498 devdata->dsc = kmemdup(&params->data[index], in parse_compression_parameters()
1499 sizeof(*devdata->dsc), GFP_KERNEL); in parse_compression_parameters()
1988 devdata->dsc != NULL); in parse_ddi_port()
2479 kfree(devdata->dsc); in intel_bios_driver_remove()
2768 struct dsc_compression_parameters_entry *dsc, in fill_dsc() argument
2771 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc()
2774 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()
2775 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()
2777 if (dsc->support_12bpc && dsc_max_bpc >= 12) in fill_dsc()
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Dicl_dsi.c364 if (crtc_state->dsc.compression_enable) in afe_clk()
365 bpp = crtc_state->dsc.compressed_bpp; in afe_clk()
784 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
924 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
925 mul = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
948 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
949 bpp = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
1499 if (pipe_config->dsc.compressed_bpp) { in gen11_dsi_get_timings()
1500 int div = pipe_config->dsc.compressed_bpp; in gen11_dsi_get_timings()
1609 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
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Dintel_dp.c729 bool dsc = false, bigjoiner = false; in intel_dp_mode_valid() local
802 dsc = dsc_max_output_bpp && dsc_slice_count; in intel_dp_mode_valid()
809 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) in intel_dp_mode_valid()
812 if (mode_rate > max_rate && !dsc) in intel_dp_mode_valid()
1131 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params()
1228 pipe_config->dsc.compressed_bpp = in intel_dp_dsc_compute_config()
1231 pipe_config->dsc.slice_count = in intel_dp_dsc_compute_config()
1234 if (!pipe_config->dsc.slice_count) { in intel_dp_dsc_compute_config()
1236 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
1261 pipe_config->dsc.compressed_bpp = min_t(u16, in intel_dp_dsc_compute_config()
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/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_hwss.c393 dsc->ctx->logger
394 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
433 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dp_set_dsc_on_stream() local
457 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in dp_set_dsc_on_stream()
458 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in dp_set_dsc_on_stream()
460 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in dp_set_dsc_on_stream()
473 dsc_optc_config_log(dsc, &dsc_optc_cfg); in dp_set_dsc_on_stream()
484 dsc_optc_config_log(dsc, &dsc_optc_cfg); in dp_set_dsc_on_stream()
508 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in dp_set_dsc_on_stream()
510 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in dp_set_dsc_on_stream()
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/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddsc.h96 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
97 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
98 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
100 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
102 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
103 void (*dsc_disable)(struct display_stream_compressor *dsc);
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c1302 struct display_stream_compressor *dsc; in dp_dsc_clock_en_read() local
1328 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1329 if (dsc) in dp_dsc_clock_en_read()
1330 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_clock_en_read()
1493 struct display_stream_compressor *dsc; in dp_dsc_slice_width_read() local
1519 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read()
1520 if (dsc) in dp_dsc_slice_width_read()
1521 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_width_read()
1682 struct display_stream_compressor *dsc; in dp_dsc_slice_height_read() local
1708 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read()
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/drivers/net/ethernet/broadcom/
Dsb1250-mac.c775 struct sbdmadscr *dsc; in sbdma_add_rcvbuffer() local
782 dsc = d->sbdma_addptr; in sbdma_add_rcvbuffer()
839 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
842 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
848 dsc->dscr_b = 0; in sbdma_add_rcvbuffer()
854 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; in sbdma_add_rcvbuffer()
889 struct sbdmadscr *dsc; in sbdma_add_txbuffer() local
897 dsc = d->sbdma_addptr; in sbdma_add_txbuffer()
928 dsc->dscr_a = phys | in sbdma_add_txbuffer()
937 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | in sbdma_add_txbuffer()
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/drivers/net/ethernet/mellanox/mlx5/core/
Den_stats.h36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ argument
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ argument
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ argument
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ argument
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c60 const struct display_stream_compressor *dsc,
341 const struct display_stream_compressor *dsc, in dc_dsc_compute_bandwidth_range() argument
354 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_bandwidth_range()
371 const struct display_stream_compressor *dsc, in get_dsc_enc_caps() argument
378 if (dsc) { in get_dsc_enc_caps()
379 if (!dsc->ctx->dc->debug.disable_dsc) in get_dsc_enc_caps()
380 dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); in get_dsc_enc_caps()
381 if (dsc->ctx->dc->debug.native422_support) in get_dsc_enc_caps()
974 const struct display_stream_compressor *dsc, in dc_dsc_compute_config() argument
985 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_config()
DMakefile6 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
/drivers/gpu/drm/amd/display/dc/
Ddc_dsc.h64 const struct display_stream_compressor *dsc,
73 const struct display_stream_compressor *dsc,
/drivers/atm/
Dzatm.h99 u32 *dsc; /* pointer to skb's descriptor */ member
102 #define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
Dzatm.c637 u32 *dsc; in do_tx() local
653 dsc = zatm_vcc->ring+zatm_vcc->ring_curr; in do_tx()
656 dsc[1] = 0; in do_tx()
657 dsc[2] = skb->len; in do_tx()
658 dsc[3] = virt_to_bus(skb->data); in do_tx()
660 dsc[0] = uPD98401_TXPD_V | uPD98401_TXPD_DP | uPD98401_TXPD_SM in do_tx()
664 EVENT("dsc (0x%lx)\n",(unsigned long) dsc,0); in do_tx()
668 dsc = NULL; in do_tx()
673 dsc = kmalloc(uPD98401_TXPD_SIZE * 2 + in do_tx()
675 if (!dsc) { in do_tx()
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/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
Dtls_stats.c55 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
56 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
Dipsec_stats.c71 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
72 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
/drivers/gpu/drm/amd/display/dc/dml/
DMakefile73 CFLAGS_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_ccflags)
88 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags)
104 DML += dsc/rc_calc_fpu.o
/drivers/irqchip/
Dirq-partition-percpu.c235 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
237 if (dsc) in partition_get_domain()
238 return dsc->domain; in partition_get_domain()
/drivers/usb/atm/
Dueagle-atm.c1966 struct cmv_dsc_e1 *dsc = &sc->cmv_dsc.e1; in uea_dispatch_cmv_e1() local
1979 if (cmv->bFunction != dsc->function) { in uea_dispatch_cmv_e1()
1982 cmv->wIndex = cpu_to_le16(dsc->idx); in uea_dispatch_cmv_e1()
1983 put_unaligned_le32(dsc->address, in uea_dispatch_cmv_e1()
1985 cmv->wOffsetAddress = cpu_to_le16(dsc->offset); in uea_dispatch_cmv_e1()
1998 if (le16_to_cpu(cmv->wIndex) != dsc->idx || in uea_dispatch_cmv_e1()
1999 get_unaligned_le32(&cmv->dwSymbolicAddress) != dsc->address || in uea_dispatch_cmv_e1()
2000 le16_to_cpu(cmv->wOffsetAddress) != dsc->offset) in uea_dispatch_cmv_e1()
2028 struct cmv_dsc_e4 *dsc = &sc->cmv_dsc.e4; in uea_dispatch_cmv_e4() local
2037 if (be16_to_cpu(cmv->wFunction) != dsc->function) in uea_dispatch_cmv_e4()
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/drivers/media/platform/s5p-mfc/
Ds5p_mfc_opr_v5.c40 ctx->dsc.size = buf_size->dsc; in s5p_mfc_alloc_dec_temp_buffers_v5()
41 ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->dsc); in s5p_mfc_alloc_dec_temp_buffers_v5()
47 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); in s5p_mfc_alloc_dec_temp_buffers_v5()
48 memset(ctx->dsc.virt, 0, ctx->dsc.size); in s5p_mfc_alloc_dec_temp_buffers_v5()
57 s5p_mfc_release_priv_buf(ctx->dev, &ctx->dsc); in s5p_mfc_release_dec_desc_buffer_v5()
350 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); in s5p_mfc_set_dec_desc_buffer()
351 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); in s5p_mfc_set_dec_desc_buffer()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c637 .dsc = {
740 .dsc = {
932 .dsc = {
1128 .dsc = {
/drivers/gpu/drm/selftests/
Dtest-drm_dp_mst_helper.c23 bool dsc; in igt_dp_mst_calc_pbn_mode() member
35 test_params[i].dsc); in igt_dp_mst_calc_pbn_mode()

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