| /drivers/gpu/drm/ |
| D | drm_dsc.c | 97 const struct drm_dsc_config *dsc_cfg) in drm_dsc_pps_payload_pack() argument
109 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
110 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
116 dsc_cfg->line_buf_depth | in drm_dsc_pps_payload_pack()
117 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; in drm_dsc_pps_payload_pack()
121 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> in drm_dsc_pps_payload_pack()
123 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | in drm_dsc_pps_payload_pack()
124 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | in drm_dsc_pps_payload_pack()
125 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | in drm_dsc_pps_payload_pack()
126 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; in drm_dsc_pps_payload_pack()
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| /drivers/gpu/drm/amd/display/dc/dsc/ |
| D | rc_calc_dpi.c | 71 static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_params *rc) in copy_rc_to_cfg() argument
75 dsc_cfg->rc_quant_incr_limit0 = rc->rc_quant_incr_limit0; in copy_rc_to_cfg()
76 dsc_cfg->rc_quant_incr_limit1 = rc->rc_quant_incr_limit1; in copy_rc_to_cfg()
77 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
78 dsc_cfg->initial_xmit_delay = rc->initial_xmit_delay; in copy_rc_to_cfg()
79 dsc_cfg->first_line_bpg_offset = rc->first_line_bpg_offset; in copy_rc_to_cfg()
80 dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset; in copy_rc_to_cfg()
81 dsc_cfg->flatness_min_qp = rc->flatness_min_qp; in copy_rc_to_cfg()
82 dsc_cfg->flatness_max_qp = rc->flatness_max_qp; in copy_rc_to_cfg()
84 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; in copy_rc_to_cfg()
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| D | dc_dsc.c | 77 struct dc_dsc_config *dsc_cfg);
764 struct dc_dsc_config *dsc_cfg) in setup_dsc_config() argument
780 memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); in setup_dsc_config()
802 dsc_cfg->ycbcr422_simple = false; in setup_dsc_config()
820 dsc_cfg->ycbcr422_simple = is_dsc_possible; in setup_dsc_config()
918 dsc_cfg->num_slices_h = num_slices_h; in setup_dsc_config()
942 dsc_cfg->num_slices_v = pic_height/slice_height; in setup_dsc_config()
952 dsc_cfg->bits_per_pixel = target_bpp; in setup_dsc_config()
960 dsc_cfg->block_pred_enable = dsc_common_caps.is_block_pred_supported; in setup_dsc_config()
961 dsc_cfg->linebuf_depth = dsc_common_caps.lb_bit_depth; in setup_dsc_config()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dsc.c | 31 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_val…
42 …bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
43 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
45 …cked_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_pac…
168 … bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) in dsc2_validate_stream() argument
173 if (dsc_cfg->pic_width > dsc20->max_image_width) in dsc2_validate_stream()
176 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); in dsc2_validate_stream()
191 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, in dsc2_set_config() argument
199 dsc_config_log(dsc, dsc_cfg); in dsc2_set_config()
200 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); in dsc2_set_config()
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| D | dcn20_resource.c | 2037 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h; in dcn20_populate_dml_pipes_from_context()
2174 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple) in dcn20_populate_dml_pipes_from_context()
2186 …pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.… in dcn20_populate_dml_pipes_from_context()
2459 struct dsc_config dsc_cfg; in dcn20_validate_dsc() local
2470 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left in dcn20_validate_dsc()
2472 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top in dcn20_validate_dsc()
2474 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in dcn20_validate_dsc()
2475 dsc_cfg.color_depth = stream->timing.display_color_depth; in dcn20_validate_dsc()
2476 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in dcn20_validate_dsc()
2477 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in dcn20_validate_dsc()
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| D | dcn20_stream_encoder.c | 442 && !timing->dsc_cfg.ycbcr422_simple); in is_two_pixels_per_containter()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_hwss.c | 443 struct dsc_config dsc_cfg; in dp_set_dsc_on_stream() local
448 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in dp_set_dsc_on_stream()
449 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in dp_set_dsc_on_stream()
450 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in dp_set_dsc_on_stream()
451 dsc_cfg.color_depth = stream->timing.display_color_depth; in dp_set_dsc_on_stream()
452 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in dp_set_dsc_on_stream()
453 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in dp_set_dsc_on_stream()
454 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in dp_set_dsc_on_stream()
455 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dp_set_dsc_on_stream()
457 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in dp_set_dsc_on_stream()
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| D | dc_stream.c | 109 memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); in dc_stream_construct()
110 stream->timing.dsc_cfg.num_slices_h = 0; in dc_stream_construct()
111 stream->timing.dsc_cfg.num_slices_v = 0; in dc_stream_construct()
112 stream->timing.dsc_cfg.bits_per_pixel = 128; in dc_stream_construct()
113 stream->timing.dsc_cfg.block_pred_enable = 1; in dc_stream_construct()
114 stream->timing.dsc_cfg.linebuf_depth = 9; in dc_stream_construct()
115 stream->timing.dsc_cfg.version_minor = 2; in dc_stream_construct()
116 stream->timing.dsc_cfg.ycbcr422_simple = 0; in dc_stream_construct()
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| D | dc_link.c | 3739 timing->dsc_cfg.bits_per_pixel, in dc_bandwidth_in_kbps_from_timing()
3740 timing->dsc_cfg.num_slices_h, in dc_bandwidth_in_kbps_from_timing()
3741 timing->dsc_cfg.is_dp); in dc_bandwidth_in_kbps_from_timing()
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| D | dc.c | 2522 struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; in copy_stream_update_to_stream()
2533 stream->timing.dsc_cfg = *update->dsc_config; in copy_stream_update_to_stream()
2536 stream->timing.dsc_cfg = old_dsc_cfg; in copy_stream_update_to_stream()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dsc.h | 97 …ol (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
98 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
100 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_mst_types.c | 617 memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); in set_dsc_configs_from_fairness_vars()
625 ¶ms[i].timing->dsc_cfg)) { in set_dsc_configs_from_fairness_vars()
629 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite; in set_dsc_configs_from_fairness_vars()
631 params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16; in set_dsc_configs_from_fairness_vars()
634 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h; in set_dsc_configs_from_fairness_vars()
637 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v; in set_dsc_configs_from_fairness_vars()
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| D | amdgpu_dm.c | 6122 &stream->timing.dsc_cfg)) { in apply_dsc_policy_for_stream()
6133 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h; in apply_dsc_policy_for_stream()
6136 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; in apply_dsc_policy_for_stream()
6139 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel; in apply_dsc_policy_for_stream()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_dsc.h | 79 struct dc_dsc_config *dsc_cfg);
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| D | dc_hw_types.h | 777 struct dc_dsc_config dsc_cfg; member
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dccg.c | 136 && !timing->dsc_cfg.ycbcr422_simple)) { in dccg31_set_dtbclk_dto()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 1617 && !timing->dsc_cfg.ycbcr422_simple); in optc1_is_two_pixels_per_containter()
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