Searched refs:dscclk_mhz (Results 1 – 10 of 10) sorted by relevance
/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_resource.c | 176 .dscclk_mhz = 205.67, 187 .dscclk_mhz = 205.67, 198 .dscclk_mhz = 287.67, 209 .dscclk_mhz = 318.334, 220 .dscclk_mhz = 489.0, 231 .dscclk_mhz = 287.67, 242 .dscclk_mhz = 318.334, 253 .dscclk_mhz = 489.0, 265 .dscclk_mhz = 489.0, 1578 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz; in construct_low_pstate_lvl() [all …]
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/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_socbb.h | 28 uint32_t dscclk_mhz; member
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/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_resource.c | 241 .dscclk_mhz = 171.0, 252 .dscclk_mhz = 214.0, 263 .dscclk_mhz = 245.0, 274 .dscclk_mhz = 367.0, 285 .dscclk_mhz = 428.0, 297 .dscclk_mhz = 428.0, 352 .dscclk_mhz = 171.0, 363 .dscclk_mhz = 214.0, 374 .dscclk_mhz = 245.0, 385 .dscclk_mhz = 367.0, [all …]
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/drivers/gpu/drm/amd/display/dc/dcn301/ |
D | dcn301_resource.c | 176 .dscclk_mhz = 206.0, 187 .dscclk_mhz = 206.0, 198 .dscclk_mhz = 296.0, 210 .dscclk_mhz = 338.0, 222 .dscclk_mhz = 338.0, 1608 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn301_update_bw_bounding_box()
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/drivers/gpu/drm/amd/display/dc/dcn31/ |
D | dcn31_resource.c | 177 .dscclk_mhz = 186.0, 186 .dscclk_mhz = 209.0, 195 .dscclk_mhz = 209.0, 204 .dscclk_mhz = 371.0, 213 .dscclk_mhz = 417.0, 1913 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn31_update_bw_bounding_box()
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/drivers/gpu/drm/amd/display/dc/dml/ |
D | display_mode_structs.h | 59 double dscclk_mhz; member
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D | display_mode_vba.c | 285 mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz; in fetch_socbb_params()
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/drivers/gpu/drm/amd/display/dc/dcn302/ |
D | dcn302_resource.c | 161 .dscclk_mhz = 405.6, 1417 dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz; in dcn302_update_bw_bounding_box()
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/drivers/gpu/drm/amd/display/dc/dcn303/ |
D | dcn303_resource.c | 143 .dscclk_mhz = 405.6, 1345 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; in dcn303_update_bw_bounding_box()
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/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_resource.c | 179 .dscclk_mhz = 405.6, 2511 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz; in dcn30_update_bw_bounding_box()
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