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Searched refs:dst_w (Results 1 – 25 of 34) sorted by relevance

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/drivers/media/platform/ti-vpe/
Dsc.c62 unsigned int dst_w) in sc_set_hs_coeffs() argument
70 if (dst_w > src_w) { in sc_set_hs_coeffs()
73 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
74 dst_w <<= 1; /* first level decimation */ in sc_set_hs_coeffs()
75 if ((dst_w << 1) < src_w) in sc_set_hs_coeffs()
76 dst_w <<= 1; /* second level decimation */ in sc_set_hs_coeffs()
78 if (dst_w == src_w) { in sc_set_hs_coeffs()
81 sixteenths = (dst_w << 4) / src_w; in sc_set_hs_coeffs()
149 unsigned int dst_w, unsigned int dst_h) in sc_config_scaler() argument
178 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
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Dsc.h200 unsigned int dst_w);
205 unsigned int dst_w, unsigned int dst_h);
/drivers/media/pci/ivtv/
Divtv-yuv.c224 f->tru_w, f->src_w, f->dst_w, f->src_x, f->dst_x); in ivtv_yuv_handle_horizontal()
230 reg_2834 = f->dst_w; in ivtv_yuv_handle_horizontal()
246 if ((f->tru_x - f->pan_x > -1) && (f->tru_x - f->pan_x <= 40) && (f->dst_w >= 680)) in ivtv_yuv_handle_horizontal()
248 else if ((f->tru_x - f->pan_x < 0) && (f->tru_x - f->pan_x >= -20) && (f->dst_w >= 660)) in ivtv_yuv_handle_horizontal()
251 if (f->dst_w >= f->src_w) in ivtv_yuv_handle_horizontal()
257 if (f->dst_w < f->src_w) in ivtv_yuv_handle_horizontal()
263 reg_2870_offset = (f->src_x * ((f->dst_w << 21) / f->src_w)) >> 19; in ivtv_yuv_handle_horizontal()
265 if (f->dst_w >= f->src_w) { in ivtv_yuv_handle_horizontal()
267 master_width = (f->src_w * 0x00200000) / (f->dst_w); in ivtv_yuv_handle_horizontal()
268 if (master_width * f->dst_w != f->src_w * 0x00200000) in ivtv_yuv_handle_horizontal()
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/drivers/gpu/drm/zte/
Dzx_plane.c150 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
159 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_vl_rsz_setup()
175 zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w)); in zx_vl_rsz_setup()
177 zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w)); in zx_vl_rsz_setup()
198 u32 dst_x, dst_y, dst_w, dst_h; in zx_vl_plane_atomic_update() local
215 dst_w = drm_rect_width(dst); in zx_vl_plane_atomic_update()
237 GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h)); in zx_vl_plane_atomic_update()
252 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
346 u32 dst_w, u32 dst_h) in zx_gl_rsz_setup() argument
351 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_gl_rsz_setup()
[all …]
/drivers/gpu/drm/sti/
Dsti_hqvdp.c480 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
519 dst_w = c->hvsrc.output_picture_size & 0x0000FFFF; in hqvdp_dbg_dump_cmd()
521 seq_printf(s, "\t%dx%d", dst_w, dst_h); in hqvdp_dbg_dump_cmd()
534 if (dst_w > src_w) in hqvdp_dbg_dump_cmd()
535 seq_printf(s, " %d/1", dst_w / src_w); in hqvdp_dbg_dump_cmd()
537 seq_printf(s, " 1/%d", src_w / dst_w); in hqvdp_dbg_dump_cmd()
735 int dst_w, int dst_h) in sti_hqvdp_check_hw_scaling() argument
741 lfw /= max(src_w, dst_w) * mode->clock / 1000; in sti_hqvdp_check_hw_scaling()
1030 int dst_x, dst_y, dst_w, dst_h; in sti_hqvdp_atomic_check() local
1041 dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x); in sti_hqvdp_atomic_check()
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Dsti_vid.c146 int dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); in sti_vid_commit() local
153 dst_w = ALIGN(dst_w, 2); in sti_vid_commit()
164 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); in sti_vid_commit()
Dsti_gdp.c629 int dst_x, dst_y, dst_w, dst_h; in sti_gdp_atomic_check() local
642 dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x); in sti_gdp_atomic_check()
695 dst_w, dst_h, dst_x, dst_y, in sti_gdp_atomic_check()
713 int dst_x, dst_y, dst_w, dst_h; in sti_gdp_atomic_update() local
756 dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x); in sti_gdp_atomic_update()
792 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); in sti_gdp_atomic_update()
797 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); in sti_gdp_atomic_update()
802 src_w = dst_w; in sti_gdp_atomic_update()
Dsti_cursor.c194 int dst_x, dst_y, dst_w, dst_h; in sti_cursor_atomic_check() local
205 dst_w = clamp_val(new_plane_state->crtc_w, 0, in sti_cursor_atomic_check()
253 DRM_DEBUG_KMS("(%dx%d)@(%d,%d)\n", dst_w, dst_h, dst_x, dst_y); in sti_cursor_atomic_check()
/drivers/media/platform/rockchip/rga/
Drga-hw.c166 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y; in rga_cmd_set_trans_info() local
185 dst_w = ctx->out.crop.width; in rga_cmd_set_trans_info()
262 if (dst_w == src_h) in rga_cmd_set_trans_info()
268 scale_dst_h = dst_w; in rga_cmd_set_trans_info()
271 scale_dst_w = dst_w; in rga_cmd_set_trans_info()
313 dst_act_info.data.act_width = dst_w - 1; in rga_cmd_set_trans_info()
324 offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h); in rga_cmd_set_trans_info()
/drivers/gpu/drm/meson/
Dmeson_plane.c147 int src_w, src_h, dst_w, dst_h; in meson_plane_atomic_update() local
265 dst_w = new_state->crtc_w; in meson_plane_atomic_update()
281 hf_phase_step = ((src_w << 18) / dst_w) << 6; in meson_plane_atomic_update()
292 if (src_h != dst_h || src_w != dst_w) { in meson_plane_atomic_update()
331 if (src_w != dst_w) { in meson_plane_atomic_update()
362 priv->viu.osb_blend0_size = dst_h << 16 | dst_w; in meson_plane_atomic_update()
363 priv->viu.osb_blend1_size = dst_h << 16 | dst_w; in meson_plane_atomic_update()
/drivers/gpu/drm/sun4i/
Dsun8i_ui_layer.c101 u32 src_w, src_h, dst_w, dst_h; in sun8i_ui_layer_update_coord() local
114 dst_w = drm_rect_width(&state->dst); in sun8i_ui_layer_update_coord()
121 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); in sun8i_ui_layer_update_coord()
128 dst_w, dst_h); in sun8i_ui_layer_update_coord()
172 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_ui_layer_update_coord()
183 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_ui_layer_update_coord()
Dsun8i_vi_layer.c105 u32 src_w, src_h, dst_w, dst_h; in sun8i_vi_layer_update_coord() local
121 dst_w = drm_rect_width(&state->dst); in sun8i_vi_layer_update_coord()
147 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); in sun8i_vi_layer_update_coord()
180 do_div(ability, mode->vdisplay * fps * max(src_w, dst_w)); in sun8i_vi_layer_update_coord()
201 hscale = (src_w << 16) / dst_w; in sun8i_vi_layer_update_coord()
204 sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_vi_layer_update_coord()
233 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_vi_layer_update_coord()
Dsun8i_ui_scaler.c149 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_ui_scaler_setup() argument
167 outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h); in sun8i_ui_scaler_setup()
Dsun8i_vi_scaler.c927 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_vi_scaler_setup() argument
943 outsize = SUN8I_VI_SCALER_SIZE(dst_w, dst_h); in sun8i_vi_scaler_setup()
Dsun8i_ui_scaler.h40 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
Dsun8i_vi_scaler.h74 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
/drivers/gpu/drm/i915/display/
Dskl_scaler.c93 int src_w, int src_h, int dst_w, int dst_h, in skl_update_scaler() argument
109 if (src_w != dst_w || src_h != dst_h) in skl_update_scaler()
159 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || in skl_update_scaler()
162 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || in skl_update_scaler()
165 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { in skl_update_scaler()
170 dst_w, dst_h); in skl_update_scaler()
178 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
Dintel_atomic_plane.c143 unsigned int src_w, src_h, dst_w, dst_h; in intel_adjusted_rate() local
147 dst_w = drm_rect_width(dst); in intel_adjusted_rate()
151 dst_w = min(src_w, dst_w); in intel_adjusted_rate()
155 dst_w * dst_h); in intel_adjusted_rate()
/drivers/gpu/drm/
Ddrm_rect.c174 int dst_w = drm_rect_width(dst); in drm_rect_calc_hscale() local
175 int hscale = drm_calc_scale(src_w, dst_w); in drm_rect_calc_hscale()
177 if (hscale < 0 || dst_w == 0) in drm_rect_calc_hscale()
/drivers/gpu/drm/imx/dcss/
Ddcss-plane.c278 u32 src_w, src_h, dst_w, dst_h; in dcss_plane_atomic_update() local
303 dst_w = drm_rect_width(&dst); in dcss_plane_atomic_update()
330 dst_w, dst_h, in dcss_plane_atomic_update()
334 dst.x1, dst.y1, dst_w, dst_h); in dcss_plane_atomic_update()
/drivers/media/platform/sti/bdisp/
Dbdisp-hw.c630 u32 src_w, src_h, dst_w, dst_h; in bdisp_hw_get_hv_inc() local
634 dst_w = ctx->dst.crop.width; in bdisp_hw_get_hv_inc()
637 if (bdisp_hw_get_inc(src_w, dst_w, h_inc) || in bdisp_hw_get_hv_inc()
641 src_w, src_h, dst_w, dst_h); in bdisp_hw_get_hv_inc()
/drivers/gpu/drm/rockchip/
Drockchip_drm_vop.c357 uint32_t src_w, uint32_t src_h, uint32_t dst_w, in scl_vop_cal_scl_fac() argument
374 if (dst_w > 3840) { in scl_vop_cal_scl_fac()
381 scl_cal_scale2(src_w, dst_w)); in scl_vop_cal_scl_fac()
386 scl_cal_scale2(cbcr_src_w, dst_w)); in scl_vop_cal_scl_fac()
393 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); in scl_vop_cal_scl_fac()
397 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); in scl_vop_cal_scl_fac()
400 lb_mode = scl_vop_cal_lb_mode(dst_w, true); in scl_vop_cal_scl_fac()
405 lb_mode = scl_vop_cal_lb_mode(dst_w, false); in scl_vop_cal_scl_fac()
427 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, in scl_vop_cal_scl_fac()
444 dst_w, true, 0, NULL); in scl_vop_cal_scl_fac()
/drivers/gpu/drm/exynos/
Dexynos_drm_gsc.c747 u32 src_w, src_h, dst_w, dst_h; in gsc_set_prescaler() local
754 dst_w = dst->h; in gsc_set_prescaler()
757 dst_w = dst->w; in gsc_set_prescaler()
761 ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio); in gsc_set_prescaler()
776 sc->main_hratio = (src_w << 16) / dst_w; in gsc_set_prescaler()
Dexynos_drm_fimc.c744 u32 src_w, src_h, dst_w, dst_h; in fimc_set_prescaler() local
756 dst_w = dst->h; in fimc_set_prescaler()
759 dst_w = dst->w; in fimc_set_prescaler()
764 hfactor = fls(src_w / dst_w / 2); in fimc_set_prescaler()
783 sc->hratio = (src_w << 14) / (dst_w << hfactor); in fimc_set_prescaler()
785 sc->up_h = (dst_w >= src_w) ? true : false; in fimc_set_prescaler()
/drivers/gpu/drm/tegra/
Dplane.c254 unsigned int i, bpp, dst_w, dst_h, src_w, src_h, mul; in tegra_plane_calculate_memory_bandwidth() local
269 dst_w = drm_rect_width(&state->dst); in tegra_plane_calculate_memory_bandwidth()
296 avg_bandwidth = min(src_w, dst_w) * min(src_h, dst_h); in tegra_plane_calculate_memory_bandwidth()

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