Searched refs:dstate (Results 1 – 4 of 4) sorted by relevance
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
D | base.c | 312 clk->astate, clk->temp, clk->dstate); in nvkm_pstate_work() 318 pstate = max(pstate, clk->dstate); in nvkm_pstate_work() 555 if (!rel) clk->dstate = req; in nvkm_clk_dstate() 556 if ( rel) clk->dstate += rel; in nvkm_clk_dstate() 557 clk->dstate = min(clk->dstate, clk->state_nr - 1); in nvkm_clk_dstate() 558 clk->dstate = max(clk->dstate, 0); in nvkm_clk_dstate() 619 clk->dstate = 0; in nvkm_clk_init()
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/drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
D | clk.h | 103 int dstate; /* display adjustment (min+) */ member
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/drivers/staging/rts5208/ |
D | rtsx_chip.c | 1728 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate) in rtsx_handle_pm_dstate() argument 1733 chip->product_id, dstate); in rtsx_handle_pm_dstate() 1746 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate); in rtsx_handle_pm_dstate() 1749 rtsx_write_config_byte(chip, 0x44, dstate); in rtsx_handle_pm_dstate()
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/drivers/gpu/drm/i915/ |
D | intel_pm.c | 7982 u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE); in gen3_init_clock_gating() local 7984 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | in gen3_init_clock_gating() 7986 intel_uncore_write(&dev_priv->uncore, D_STATE, dstate); in gen3_init_clock_gating()
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