Home
last modified time | relevance | path

Searched refs:dwb_pipe_inst (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c227 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn30_set_writeback()
231 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
236 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
239 …config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); in dcn30_set_writeback()
248 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
250 __func__, wb_info->dwb_pipe_inst,\ in dcn30_update_writeback()
270 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
299 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
300 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
326 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
[all …]
Ddcn30_hwseq.h48 unsigned int dwb_pipe_inst);
/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c445 if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_add_writeback()
452 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
460 stream->writeback_info[i].dwb_pipe_inst == wb_info->dwb_pipe_inst) { in dc_stream_add_writeback()
472 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
483 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
499 uint32_t dwb_pipe_inst) in dc_stream_remove_writeback() argument
507 if (dwb_pipe_inst >= MAX_DWB_PIPES) { in dc_stream_remove_writeback()
516 stream->writeback_info[i].dwb_pipe_inst == dwb_pipe_inst) { in dc_stream_remove_writeback()
541 dc->hwss.disable_writeback(dc, dwb_pipe_inst); in dc_stream_remove_writeback()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c284 uint32_t dwb_pipe_inst) in optc2_set_dwb_source() argument
288 if (dwb_pipe_inst == 0) in optc2_set_dwb_source()
291 else if (dwb_pipe_inst == 1) in optc2_set_dwb_source()
Ddcn20_hwseq.h110 unsigned int dwb_pipe_inst);
Ddcn20_hwseq.c1938 ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_enable_writeback()
1940 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
1941 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn20_enable_writeback()
1945 optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst); in dcn20_enable_writeback()
1948 …config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]); in dcn20_enable_writeback()
1958 unsigned int dwb_pipe_inst) in dcn20_disable_writeback() argument
1963 ASSERT(dwb_pipe_inst < MAX_DWB_PIPES); in dcn20_disable_writeback()
1964 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn20_disable_writeback()
1965 mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst]; in dcn20_disable_writeback()
/drivers/gpu/drm/amd/display/dc/
Ddc_stream.h88 int dwb_pipe_inst; member
397 uint32_t dwb_pipe_inst);
/drivers/gpu/drm/amd/display/dc/inc/
Dhw_sequencer.h176 unsigned int dwb_pipe_inst);
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtiming_generator.h257 uint32_t dwb_pipe_inst);