| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_rq_dlg_calc_31.c | 941 const display_e2e_pipe_params_st *e2e_pipe_param, in dml_rq_dlg_get_dlg_params() argument
954 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
955 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
956 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
957 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
958 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
959 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1050 …int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pi… in dml_rq_dlg_get_dlg_params()
1051 …int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, nu… in dml_rq_dlg_get_dlg_params()
1053 …_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pi… in dml_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_31.h | 60 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1003 const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param, in dml1_rq_dlg_get_dlg_params() argument
1010 unsigned int htotal = e2e_pipe_param.pipe.dest.htotal; in dml1_rq_dlg_get_dlg_params()
1011 unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end; in dml1_rq_dlg_get_dlg_params()
1012 unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start; in dml1_rq_dlg_get_dlg_params()
1013 unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params()
1014 bool interlaced = e2e_pipe_param.pipe.dest.interlaced; in dml1_rq_dlg_get_dlg_params()
1017 double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz; in dml1_rq_dlg_get_dlg_params()
1018 double refclk_freq_in_mhz = e2e_pipe_param.clks_cfg.refclk_mhz; in dml1_rq_dlg_get_dlg_params()
1019 double dppclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params()
1020 double dispclk_freq_in_mhz = e2e_pipe_param.clks_cfg.dispclk_mhz; in dml1_rq_dlg_get_dlg_params()
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| D | dml1_display_rq_dlg_calc.h | 60 const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
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| D | display_mode_lib.h | 52 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 982 const display_e2e_pipe_params_st *e2e_pipe_param, in dml_rq_dlg_get_dlg_params() argument
995 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
996 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
997 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
998 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
999 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
1000 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1141 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
1142 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1217 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_30.h | 60 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 47 const display_e2e_pipe_params_st *e2e_pipe_param,
785 const display_e2e_pipe_params_st *e2e_pipe_param, in dml20v2_rq_dlg_get_dlg_params() argument
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20v2_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20v2_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20v2_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.c | 47 const display_e2e_pipe_params_st *e2e_pipe_param,
785 const display_e2e_pipe_params_st *e2e_pipe_param, in dml20_rq_dlg_get_dlg_params() argument
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| D | display_rq_dlg_calc_20v2.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 831 const display_e2e_pipe_params_st *e2e_pipe_param, in dml_rq_dlg_get_dlg_params() argument
841 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
845 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
985 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_21.h | 64 const display_e2e_pipe_params_st *e2e_pipe_param,
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