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Searched refs:engineClock (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_processpptables.c210 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; in init_powerplay_table_information()
212 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_powerplay_table_information()
230 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_powerplay_table_information()
Dsmu8_hwmgr.c417 data->boot_power_level.engineClock = in smu8_construct_boot_state()
1343 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()
1345 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()
1379 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()
1600 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1604 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()
1605 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
1628 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()
1629 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1]… in smu8_get_current_shallow_sleep_clocks()
Dvega10_hwmgr.c912 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()
1355 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()
1356 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()
1616 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()
3284 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3315 minimum_clocks.engineClock = stable_pstate_sclk; in vega10_apply_state_adjust_rules()
3337 if (sclk < minimum_clocks.engineClock) in vega10_apply_state_adjust_rules()
3338 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in vega10_apply_state_adjust_rules()
3339 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()
4745 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_print_clock_levels()
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Dsmu8_hwmgr.h100 uint32_t engineClock; member
Dsmu7_hwmgr.c912 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in smu7_setup_dpm_tables_v1()
913 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()
2965 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()
3320 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()
3343 minimum_clocks.engineClock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()
3375 if (sclk < minimum_clocks.engineClock) in smu7_apply_state_adjust_rules()
3376 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()
3377 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()
4991 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in smu7_print_clock_levels()
5411 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in smu7_check_clk_voltage_valid()
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Dprocesspptables.c1117 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()
1155 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()
1175 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
Dvega10_processpptables.c327 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
330 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
Dsmu10_hwmgr.c571 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu10_hwmgr_backend_init()
Dprocess_pptables_v1_0.c889 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
Dvega12_hwmgr.c428 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
Dvega20_hwmgr.c470 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega20_hwmgr_backend_init()
/drivers/gpu/drm/amd/pm/inc/
Dhardwaremanager.h327 uint32_t engineClock; member
/drivers/gpu/drm/amd/display/dc/
Ddc_types.h776 unsigned int engineClock; member
/drivers/gpu/drm/amd/display/dc/core/
Ddc.c3610 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; in get_clock_requirements_for_state()