| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 141 v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ argument
152 FN(reg, f10), v10)
302 …G_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\ argument
313 FN(reg, f10), v10)
315 …ne REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ argument
327 FN(reg, f10), v10, \
333 …ne REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ argument
345 FN(reg, f10), v10, \
356 …ne REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\ argument
368 FN(reg, f10), v10, \
|
| /drivers/pinctrl/qcom/ |
| D | pinctrl-ipq8064.c | 171 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ argument
187 IPQ_MUX_##f10, \
|
| D | pinctrl-apq8064.c | 219 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ argument
235 APQ_MUX_##f10, \
|
| D | pinctrl-mdm9615.c | 205 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ argument
221 MSM_MUX_##f10, \
|
| D | pinctrl-ipq4019.c | 226 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14) \ argument
242 qca_mux_##f10, \
|
| D | pinctrl-msm8960.c | 344 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ argument
360 MSM_MUX_##f10, \
|
| D | pinctrl-msm8994.c | 20 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \ argument
36 MSM_MUX_##f10, \
|
| D | pinctrl-sdm845.c | 25 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ argument
41 msm_mux_##f10 \
|