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Searched refs:full_recout_width (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c728 …ull_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; in get_surf_rq_param()
731 … full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; in get_surf_rq_param()
956 unsigned int full_recout_width; in dml_rq_dlg_get_dlg_params() local
1258 full_recout_width = 0; in dml_rq_dlg_get_dlg_params()
1263 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml_rq_dlg_get_dlg_params()
1267 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 in dml_rq_dlg_get_dlg_params()
1269 full_recout_width = dst->full_recout_width; in dml_rq_dlg_get_dlg_params()
1271 full_recout_width = dst->recout_width; in dml_rq_dlg_get_dlg_params()
1279 full_recout_width, in dml_rq_dlg_get_dlg_params()
1291 full_recout_width, in dml_rq_dlg_get_dlg_params()
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/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c910 unsigned int full_recout_width; in dml20v2_rq_dlg_get_dlg_params() local
1207 full_recout_width = 0; in dml20v2_rq_dlg_get_dlg_params()
1212 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml20v2_rq_dlg_get_dlg_params()
1215 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 in dml20v2_rq_dlg_get_dlg_params()
1217 full_recout_width = dst->full_recout_width; in dml20v2_rq_dlg_get_dlg_params()
1219 full_recout_width = dst->recout_width; in dml20v2_rq_dlg_get_dlg_params()
1226 full_recout_width, in dml20v2_rq_dlg_get_dlg_params()
1237 full_recout_width, in dml20v2_rq_dlg_get_dlg_params()
1246 full_recout_width); in dml20v2_rq_dlg_get_dlg_params()
1262 full_recout_width, in dml20v2_rq_dlg_get_dlg_params()
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Ddisplay_rq_dlg_calc_20.c910 unsigned int full_recout_width; in dml20_rq_dlg_get_dlg_params() local
1206 full_recout_width = 0; in dml20_rq_dlg_get_dlg_params()
1211 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml20_rq_dlg_get_dlg_params()
1214 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 in dml20_rq_dlg_get_dlg_params()
1216 full_recout_width = dst->full_recout_width; in dml20_rq_dlg_get_dlg_params()
1218 full_recout_width = dst->recout_width; in dml20_rq_dlg_get_dlg_params()
1225 full_recout_width, in dml20_rq_dlg_get_dlg_params()
1236 full_recout_width, in dml20_rq_dlg_get_dlg_params()
1245 full_recout_width); in dml20_rq_dlg_get_dlg_params()
1261 full_recout_width, in dml20_rq_dlg_get_dlg_params()
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/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c777 …ull_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; in get_surf_rq_param()
780 … full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; in get_surf_rq_param()
1045 unsigned int full_recout_width; in dml_rq_dlg_get_dlg_params() local
1312 full_recout_width = 0; in dml_rq_dlg_get_dlg_params()
1317 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml_rq_dlg_get_dlg_params()
1319 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 in dml_rq_dlg_get_dlg_params()
1321 full_recout_width = dst->full_recout_width; in dml_rq_dlg_get_dlg_params()
1323 full_recout_width = dst->recout_width; in dml_rq_dlg_get_dlg_params()
1331 full_recout_width, in dml_rq_dlg_get_dlg_params()
1343 full_recout_width, in dml_rq_dlg_get_dlg_params()
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/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c785 …ull_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio_c * pipe_param->dest.full_recout_width; in get_surf_rq_param()
788 … full_src_vp_width = pipe_param->scale_ratio_depth.hscl_ratio * pipe_param->dest.full_recout_width; in get_surf_rq_param()
1110 unsigned int full_recout_width = 0; in dml_rq_dlg_get_dlg_params() local
1448 full_recout_width = 0; in dml_rq_dlg_get_dlg_params()
1453 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml_rq_dlg_get_dlg_params()
1456 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 in dml_rq_dlg_get_dlg_params()
1458 full_recout_width = dst->full_recout_width; in dml_rq_dlg_get_dlg_params()
1460 full_recout_width = dst->recout_width; in dml_rq_dlg_get_dlg_params()
1467 full_recout_width, in dml_rq_dlg_get_dlg_params()
1478 full_recout_width, in dml_rq_dlg_get_dlg_params()
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/drivers/gpu/drm/amd/display/dc/dml/
Ddml1_display_rq_dlg_calc.c1124 unsigned int full_recout_width; in dml1_rq_dlg_get_dlg_params() local
1652 full_recout_width = 0; in dml1_rq_dlg_get_dlg_params()
1654 if (e2e_pipe_param.pipe.dest.full_recout_width == 0) { in dml1_rq_dlg_get_dlg_params()
1656 full_recout_width = e2e_pipe_param.pipe.dest.recout_width * 2; /* assume half split for dcn1 */ in dml1_rq_dlg_get_dlg_params()
1658 full_recout_width = e2e_pipe_param.pipe.dest.full_recout_width; in dml1_rq_dlg_get_dlg_params()
1660 full_recout_width = e2e_pipe_param.pipe.dest.recout_width; in dml1_rq_dlg_get_dlg_params()
1666 full_recout_width, in dml1_rq_dlg_get_dlg_params()
1676 full_recout_width, in dml1_rq_dlg_get_dlg_params()
1682 DTRACE("DLG: %s: full_recout_width = %d", __func__, full_recout_width); in dml1_rq_dlg_get_dlg_params()
1707 full_recout_width, in dml1_rq_dlg_get_dlg_params()
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Ddisplay_mode_structs.h340 unsigned int full_recout_width; member
Ddisplay_mode_lib.c198 dml_print("DML PARAMS: full_recout_width = %d\n", pipe_dest->full_recout_width); in dml_log_pipe_params()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c2225 …pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_h… in dcn20_populate_dml_pipes_from_context()
2287 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width; in dcn20_populate_dml_pipes_from_context()
2289 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2; in dcn20_populate_dml_pipes_from_context()
2291 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4; in dcn20_populate_dml_pipes_from_context()
2296 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
2301 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c428 input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width; in pipe_ctx_to_e2e_pipe_params()