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Searched refs:h_border_right (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_opp.c314 uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; in opp1_program_stereo()
Ddcn10_stream_encoder.c437 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in enc1_stream_encoder_dp_set_stream_attribute()
469 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in enc1_stream_encoder_dp_set_stream_attribute()
Ddcn10_optc.c202 patched_crtc_timing.h_border_right - in optc1_program_timing()
584 timing->h_border_right - in optc1_validate_timing()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator.c293 uint32_t hsync_offset = dc_crtc_timing->h_border_right + in dce110_timing_generator_program_timing_generator()
324 patched_crtc_timing.h_border_right; in dce110_timing_generator_program_timing_generator()
608 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_program_blanking()
670 timing->h_border_left + timing->h_border_right; in dce110_timing_generator_program_blanking()
1128 hsync_offset = timing->h_border_right + timing->h_front_porch; in dce110_timing_generator_validate_timing()
1149 timing->h_border_right - in dce110_timing_generator_validate_timing()
1160 timing->h_border_right - in dce110_timing_generator_validate_timing()
Ddce110_timing_generator_v.c249 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
289 timing->h_border_left + timing->h_border_right; in dce110_timing_generator_v_program_blanking()
Ddce110_hw_sequencer.c686 + timing->h_border_right; in dce110_enable_stream()
1279 + stream->timing.h_border_right; in build_audio_output()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_optc.c47 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) in optc31_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_hwss.c448 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in dp_set_dsc_on_stream()
554 …idth = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; in dp_set_dsc_pps_sdp()
Ddc_resource.c1041 timing->h_border_left + timing->h_border_right; in resource_build_scaling_params()
2468 - stream->timing.h_border_right + 1); in set_avi_info_frame()
Ddc.c1425 if (crtc_timing->h_border_right != hw_crtc_timing.h_border_right) in dc_validate_seamless_boot_timing()
Ddc_link_dp.c4199 pipe_ctx->stream->timing.h_border_right; in set_crtc_test_pattern()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_optc.c207 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) in optc3_set_odm_combine()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c438 uint32_t hsync_offset = timing->h_border_right + in dce120_timing_generator_program_blanking()
469 timing->h_border_left + timing->h_border_right; in dce120_timing_generator_program_blanking()
/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h750 uint32_t h_border_right; member
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c478 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; in dce110_stream_encoder_dp_set_stream_attribute()
514 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, in dce110_stream_encoder_dp_set_stream_attribute()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_optc.c223 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) in optc2_set_odm_combine()
Ddcn20_hwseq.c626 stream->timing.h_border_right; in calc_mpc_flow_ctrl_cnt()
1002 …idth = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; in dcn20_blank_pixel_data()
2427 + timing->h_border_right; in dcn20_enable_stream()
Ddcn20_resource.c2055 - timing->h_border_right; in dcn20_populate_dml_pipes_from_context()
2064 timing->h_addressable + timing->h_border_left + timing->h_border_right; in dcn20_populate_dml_pipes_from_context()
2471 + stream->timing.h_border_right) / opp_cnt; in dcn20_validate_dsc()
2675 if (timing.h_border_left + timing.h_border_right in dcn20_validate_apply_pipe_split_flags()
/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c783 pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; in setup_dsc_config()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c436 - pipe->stream->timing.h_border_right; in pipe_ctx_to_e2e_pipe_params()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm.c5839 timing_out->h_border_right = 0; in fill_stream_properties_from_drm_display_mode()