/drivers/gpu/drm/amd/display/dc/dcn30/ |
D | dcn30_hubp.c | 122 address->grph.meta_addr.high_part); in hubp3_program_surface_flip_and_addr() 131 address->grph.addr.high_part); in hubp3_program_surface_flip_and_addr() 151 address->video_progressive.chroma_meta_addr.high_part); in hubp3_program_surface_flip_and_addr() 159 address->video_progressive.luma_meta_addr.high_part); in hubp3_program_surface_flip_and_addr() 168 address->video_progressive.chroma_addr.high_part); in hubp3_program_surface_flip_and_addr() 176 address->video_progressive.luma_addr.high_part); in hubp3_program_surface_flip_and_addr() 202 address->grph_stereo.right_alpha_meta_addr.high_part); in hubp3_program_surface_flip_and_addr() 210 address->grph_stereo.right_meta_addr.high_part); in hubp3_program_surface_flip_and_addr() 220 address->grph_stereo.left_alpha_meta_addr.high_part); in hubp3_program_surface_flip_and_addr() 228 address->grph_stereo.left_meta_addr.high_part); in hubp3_program_surface_flip_and_addr() [all …]
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D | dcn30_mmhubbub.c | 83 …(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.high_part); in mmhubbub3_warmup_mcif()
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/drivers/gpu/drm/amd/display/dmub/src/ |
D | dmub_dcn30.c | 103 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load() 112 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load() 137 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows() 152 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows() 163 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows() 170 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows() 180 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows() 187 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows() 196 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_setup_windows()
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D | dmub_dcn20.c | 170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load() 179 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_backdoor_load() 206 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows() 221 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows() 233 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows() 240 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows() 250 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows() 257 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows() 266 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn20_setup_windows()
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D | dmub_dcn31.c | 157 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_backdoor_load() 166 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_backdoor_load() 188 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows() 197 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows() 206 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows() 213 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows() 222 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); in dmub_dcn31_setup_windows()
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/drivers/gpu/drm/amd/display/dc/dcn10/ |
D | dcn10_hubp.c | 398 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr() 407 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr() 427 address->video_progressive.chroma_meta_addr.high_part); in hubp1_program_surface_flip_and_addr() 435 address->video_progressive.luma_meta_addr.high_part); in hubp1_program_surface_flip_and_addr() 444 address->video_progressive.chroma_addr.high_part); in hubp1_program_surface_flip_and_addr() 452 address->video_progressive.luma_addr.high_part); in hubp1_program_surface_flip_and_addr() 478 address->grph_stereo.right_meta_addr.high_part); in hubp1_program_surface_flip_and_addr() 488 address->grph_stereo.left_meta_addr.high_part); in hubp1_program_surface_flip_and_addr() 497 address->grph_stereo.right_addr.high_part); in hubp1_program_surface_flip_and_addr() 505 address->grph_stereo.left_addr.high_part); in hubp1_program_surface_flip_and_addr() [all …]
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D | dcn10_hw_sequencer.c | 2244 PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part); in mmhub_read_vm_system_aperture_settings() 2273 PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); in mmhub_read_vm_context0_settings() 2278 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part); in mmhub_read_vm_context0_settings() 2283 LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part); in mmhub_read_vm_context0_settings() 2288 PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part); in mmhub_read_vm_context0_settings()
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/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_hubp.c | 720 address->grph.meta_addr.high_part; in hubp21_program_surface_flip_and_addr() 726 address->grph.addr.high_part; in hubp21_program_surface_flip_and_addr() 737 address->video_progressive.luma_meta_addr.high_part; in hubp21_program_surface_flip_and_addr() 742 address->video_progressive.chroma_meta_addr.high_part; in hubp21_program_surface_flip_and_addr() 748 address->video_progressive.luma_addr.high_part; in hubp21_program_surface_flip_and_addr() 754 address->video_progressive.chroma_addr.high_part; in hubp21_program_surface_flip_and_addr() 769 address->grph_stereo.right_meta_addr.high_part; in hubp21_program_surface_flip_and_addr() 776 address->grph_stereo.left_meta_addr.high_part; in hubp21_program_surface_flip_and_addr() 782 address->grph_stereo.left_addr.high_part; in hubp21_program_surface_flip_and_addr() 787 address->grph_stereo.right_addr.high_part; in hubp21_program_surface_flip_and_addr()
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/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_hubp.c | 63 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part); in hubp2_set_vm_system_aperture_settings() 602 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part); in hubp2_cursor_set_attributes() 648 DMDATA_ADDRESS_HIGH, attr->address.high_part); in hubp2_dmdata_set_attributes() 747 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr() 756 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr() 776 address->video_progressive.chroma_meta_addr.high_part); in hubp2_program_surface_flip_and_addr() 784 address->video_progressive.luma_meta_addr.high_part); in hubp2_program_surface_flip_and_addr() 793 address->video_progressive.chroma_addr.high_part); in hubp2_program_surface_flip_and_addr() 801 address->video_progressive.luma_addr.high_part); in hubp2_program_surface_flip_and_addr() 827 address->grph_stereo.right_meta_addr.high_part); in hubp2_program_surface_flip_and_addr() [all …]
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/drivers/gpu/drm/amd/display/dc/inc/ |
D | compressor.h | 43 int32_t high_part; member
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/drivers/gpu/drm/amd/amdkfd/ |
D | kfd_dbgdev.h | 183 uint32_t high_part; member
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D | kfd_dbgdev.c | 94 ib_packet->bitfields3.ib_base_hi = largep->u.high_part; in dbgdev_diq_submit_ib() 141 rm_packet->address_hi = addr.u.high_part; in dbgdev_diq_submit_ib() 252 addrHi->bitfields.addr = addr.u.high_part & in dbgdev_address_watch_set_registers()
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/drivers/gpu/drm/amd/display/dc/ |
D | dc_hw_types.h | 48 int32_t high_part; member 53 int32_t high_part; member
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/drivers/gpu/drm/amd/display/dc/dce/ |
D | dce_ipp.c | 130 CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part); in dce_ipp_cursor_set_attributes()
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D | dce_mem_input.c | 803 address.high_part); in program_sec_addr() 817 address.high_part); in program_pri_addr()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
D | dcn31_clk_mgr.c | 482 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges() 502 smu_dpm_clks->mc_address.high_part); in dcn31_get_dpm_table_from_smu()
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/drivers/gpu/drm/amd/display/dc/dce110/ |
D | dce110_mem_input_v.c | 67 temp = address.high_part & in program_pri_addr_c() 103 temp = address.high_part & in program_pri_addr_l()
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D | dce110_compressor.c | 320 compressor->compr_surface_address.addr.high_part); in dce110_compressor_program_compressed_surface_address_and_pitch()
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D | dce110_hw_sequencer.c | 2705 pipe_ctx->plane_state->address.grph.addr.high_part, in dce110_program_front_end_for_pipe()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
D | vg_clk_mgr.c | 471 clk_mgr_vgh->smu_wm_set.mc_address.high_part); in vg_notify_wm_ranges() 723 smu_dpm_clks->mc_address.high_part); in vg_get_dpm_table_from_smu()
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/drivers/gpu/drm/amd/display/dc/dce60/ |
D | dce60_hw_sequencer.c | 351 pipe_ctx->plane_state->address.grph.addr.high_part, in dce60_program_front_end_for_pipe()
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/drivers/gpu/drm/amd/display/dc/dce112/ |
D | dce112_compressor.c | 514 compressor->compr_surface_address.addr.high_part); in dce112_compressor_program_compressed_surface_address_and_pitch()
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/drivers/gpu/drm/amd/display/dmub/inc/ |
D | dmub_cmd.h | 188 uint32_t high_part; /**< Upper 32 bits */ member
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/drivers/gpu/drm/amd/display/amdgpu_dm/ |
D | amdgpu_dm.c | 1207 page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> in mmhub_read_system_context() 1211 page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> in mmhub_read_system_context() 1215 page_table_base.high_part = upper_32_bits(pt_base); in mmhub_read_system_context() 5273 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in fill_gfx9_plane_attributes_from_modifiers() 5318 address->grph.addr.high_part = upper_32_bits(addr); in fill_plane_buffer_attributes() 5342 address->video_progressive.luma_addr.high_part = in fill_plane_buffer_attributes() 5346 address->video_progressive.chroma_addr.high_part = in fill_plane_buffer_attributes() 8791 attributes.address.high_part = upper_32_bits(address); in handle_cursor_update() 9187 bundle->flip_addrs[planes_count].address.grph.addr.high_part, in amdgpu_dm_commit_planes()
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