Searched refs:host1x_debug_cont (Results 1 – 5 of 5) sorted by relevance
| /drivers/gpu/host1x/hw/ |
| D | debug_hw.c | 52 host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [", in show_channel_command()
58 host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff); in show_channel_command()
63 host1x_debug_cont(o, "INCR(offset=%03x, [", in show_channel_command()
66 host1x_debug_cont(o, "])\n"); in show_channel_command()
72 host1x_debug_cont(o, "NONINCR(offset=%03x, [", in show_channel_command()
75 host1x_debug_cont(o, "])\n"); in show_channel_command()
81 host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [", in show_channel_command()
84 host1x_debug_cont(o, "])\n"); in show_channel_command()
89 host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n", in show_channel_command()
94 host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4); in show_channel_command()
[all …]
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| D | debug_hw_1x06.c | 122 host1x_debug_cont(o, "%08x%s", val, in host1x_debug_show_channel_fifo()
134 host1x_debug_cont(o, ", ...])\n"); in host1x_debug_show_channel_fifo()
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| D | debug_hw_1x01.c | 112 host1x_debug_cont(o, "%08x%s", val, in host1x_debug_show_channel_fifo()
124 host1x_debug_cont(o, ", ...])\n"); in host1x_debug_show_channel_fifo()
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| /drivers/gpu/host1x/ |
| D | debug.h | 37 void __printf(2, 3) host1x_debug_cont(struct output *o, const char *fmt, ...);
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| D | debug.c | 39 void host1x_debug_cont(struct output *o, const char *fmt, ...) in host1x_debug_cont() function
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