Home
last modified time | relevance | path

Searched refs:hsync_end (Results 1 – 25 of 162) sorted by relevance

1234567

/drivers/gpu/drm/panel/
Dpanel-simple.c853 .hsync_end = 1280 + 40 + 80,
879 .hsync_end = 480 + 2 + 41,
903 .hsync_end = 800 + 0 + 255,
953 .hsync_end = 1024 + 156 + 8,
1000 .hsync_end = 1366 + 20 + 70,
1023 .hsync_end = 1366 + 48 + 32,
1051 .hsync_end = 1366 + 40 + 40,
1080 .hsync_end = 1366 + 48 + 32,
1102 .hsync_end = 1920 + 58 + 42,
1132 .hsync_end = 1920 + 172 + 80,
[all …]
Dpanel-arm-versatile.c140 .hsync_end = 320 + 6 + 6,
163 .hsync_end = 640 + 24 + 96,
185 .hsync_end = 176 + 2 + 3,
208 .hsync_end = 240 + 10 + 10,
Dpanel-tpo-tpg110.c108 .hsync_end = 800 + 40 + 1,
124 .hsync_end = 640 + 24 + 1,
140 .hsync_end = 480 + 2 + 1,
156 .hsync_end = 480 + 2 + 1,
172 .hsync_end = 400 + 20 + 1,
Dpanel-ilitek-ili9322.c545 .hsync_end = 320 + 359 + 1,
558 .hsync_end = 360 + 35 + 1,
572 .hsync_end = 320 + 38 + 1,
586 .hsync_end = 640 + 252 + 1,
599 .hsync_end = 720 + 252 + 1,
613 .hsync_end = 640 + 3 + 1,
627 .hsync_end = 720 + 3 + 1,
Dpanel-boe-tv101wum-nl6.c598 .hsync_end = 1200 + 100 + 40,
625 .hsync_end = 1200 + 60 + 24,
652 .hsync_end = 1200 + 80 + 24,
679 .hsync_end = 1200 + 60 + 4,
707 .hsync_end = 1200 + 80 + 24,
Dpanel-innolux-ej030na.c240 .hsync_end = 320 + 10 + 37,
252 .hsync_end = 320 + 10 + 37,
Dpanel-novatek-nt39016.c318 .hsync_end = 320 + 10 + 50,
330 .hsync_end = 320 + 42 + 50,
Dpanel-samsung-sofef00.c171 .hsync_end = 1080 + 112 + 16,
185 .hsync_end = 1080 + 72 + 16,
Dpanel-abt-y030xx067a.c314 .hsync_end = 320 + 10 + 37,
326 .hsync_end = 320 + 10 + 37,
Dpanel-mantix-mlaf057we51.c196 .hsync_end = 720 + 45 + 14,
211 .hsync_end = 720 + 45 + 14,
Dpanel-leadtek-ltk050h3146w.c328 .hsync_end = 720 + 42 + 8,
422 .hsync_end = 720 + 42 + 10,
/drivers/gpu/drm/i915/display/
Dintel_tv.c314 u8 hsync_end; member
388 .hsync_end = 64, .hblank_end = 124,
430 .hsync_end = 64, .hblank_end = 124,
473 .hsync_end = 64, .hblank_end = 124,
516 .hsync_end = 64, .hblank_end = 124,
559 .hsync_end = 64, .hblank_end = 128,
604 .hsync_end = 64, .hblank_end = 142,
646 .hsync_end = 64, .hblank_end = 122,
670 .hsync_end = 64, .hblank_end = 139,
694 .hsync_end = 80, .hblank_end = 300,
[all …]
/drivers/gpu/drm/gud/
Dgud_internal.h125 dst->hsync_end = cpu_to_le16(src->hsync_end); in gud_from_display_mode()
143 dst->hsync_end = le16_to_cpu(src->hsync_end); in gud_to_display_mode()
/drivers/gpu/drm/
Ddrm_modes.c278 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; in drm_cvt_mode()
279 drm_mode->hsync_start = drm_mode->hsync_end - in drm_cvt_mode()
313 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; in drm_cvt_mode()
314 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; in drm_cvt_mode()
512 drm_mode->hsync_end = drm_mode->hsync_start + hsync; in drm_gtf_mode_complex()
593 dmode->hsync_end = dmode->hsync_start + vm->hsync_len; in drm_display_mode_from_videomode()
594 dmode->htotal = dmode->hsync_end + vm->hback_porch; in drm_display_mode_from_videomode()
634 vm->hsync_len = dmode->hsync_end - dmode->hsync_start; in drm_display_mode_to_videomode()
635 vm->hback_porch = dmode->htotal - dmode->hsync_end; in drm_display_mode_to_videomode()
822 p->crtc_hsync_end = p->hsync_end; in drm_mode_set_crtcinfo()
[all …]
/drivers/gpu/drm/imx/dcss/
Ddcss-ss.c130 u16 hsync_start, hsync_end; in dcss_ss_sync_set() local
144 hsync_end = vm->hsync_len - 1; in dcss_ss_sync_set()
147 ((u32)hsync_end << SYNC_END_POS) | hsync_start, in dcss_ss_sync_set()
/drivers/gpu/drm/msm/dp/
Ddp_panel.c345 drm_mode->hdisplay, drm_mode->htotal - drm_mode->hsync_end, in dp_panel_timing_cfg()
347 drm_mode->hsync_end - drm_mode->hsync_start); in dp_panel_timing_cfg()
373 data |= drm_mode->hsync_end - drm_mode->hsync_start; in dp_panel_timing_cfg()
404 drm_mode->htotal - drm_mode->hsync_end, in dp_panel_init_panel_info()
406 drm_mode->hsync_end - drm_mode->hsync_start); in dp_panel_init_panel_info()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_vid.c47 if ((mode->htotal < mode->hsync_end) in drm_mode_to_intf_timing_params()
51 || (mode->hsync_end < mode->hsync_start) in drm_mode_to_intf_timing_params()
55 mode->hsync_start, mode->hsync_end, in drm_mode_to_intf_timing_params()
76 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
80 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start; in drm_mode_to_intf_timing_params()
269 mode.hsync_end >>= 1; in dpu_encoder_phys_vid_setup_timing_engine()
275 mode.hsync_start, mode.hsync_end); in dpu_encoder_phys_vid_setup_timing_engine()
/drivers/gpu/drm/bridge/adv7511/
Dadv7533.c34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
/drivers/media/platform/xilinx/
Dxilinx-vtc.h24 unsigned int hsync_end; member
/drivers/gpu/drm/shmobile/
Dshmob_drm_crtc.c101 value = (((mode->hsync_end - mode->hsync_start) / 8) << 16) /* HSYNW */ in shmob_drm_crtc_setup_geometry()
106 | (((mode->hsync_end - mode->hsync_start) & 7) << 8) in shmob_drm_crtc_setup_geometry()
601 mode->hsync_end = sdev->pdata->panel.mode.hsync_end; in shmob_drm_connector_get_modes()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_encoders.c173 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; in amdgpu_panel_mode_fixup()
184 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width; in amdgpu_panel_mode_fixup()
/drivers/gpu/drm/gma500/
Dintel_bios.c153 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + in fill_detail_timing_data()
180 if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) in fill_detail_timing_data()
181 panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; in fill_detail_timing_data()
/drivers/gpu/drm/tilcdc/
Dtilcdc_crtc.c314 hbp = mode->htotal - mode->hsync_end; in tilcdc_crtc_set_mode()
316 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_set_mode()
655 adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_fixup()
795 hbp = mode->htotal - mode->hsync_end; in tilcdc_crtc_mode_valid()
797 hsw = mode->hsync_end - mode->hsync_start; in tilcdc_crtc_mode_valid()
/drivers/gpu/drm/bridge/analogix/
Danx7625.c1427 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; in anx7625_bridge_mode_set()
1429 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; in anx7625_bridge_mode_set()
1452 mode->hsync_end, in anx7625_bridge_mode_set()
1474 hsync = mode->hsync_end - mode->hsync_start; in anx7625_bridge_mode_fixup()
1476 hbp = mode->htotal - mode->hsync_end; in anx7625_bridge_mode_fixup()
1483 adj->hsync_start, adj->hsync_end, adj->htotal); in anx7625_bridge_mode_fixup()
1567 adj->hsync_end = adj->hsync_start + adj_hsync; in anx7625_bridge_mode_fixup()
1568 adj->htotal = adj->hsync_end + adj_hbp; in anx7625_bridge_mode_fixup()
1570 adj->hsync_start, adj->hsync_end, adj->htotal); in anx7625_bridge_mode_fixup()
/drivers/gpu/drm/zte/
Dzx_tvenc.c71 .hsync_end = 720 + 12 + 2,
102 .hsync_end = 720 + 16 + 2,

1234567